From: "Alexandro Sanchez Bach" <alexandro@phi.nz>
Date: Sun, 1 Apr 2018 21:36:22 +0200
Message-ID: <000901d3c9f0$b7c08d60$2741a820$@phi.nz>
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Subject: [Qemu-devel] [PATCH] target/i386: Fix andn instruction
To: qemu-devel@nongnu.org
Cc: 'Paolo Bonzini' <pbonzini@redhat.com>

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In commit 7073fbada733c8d10992f00772c9b9299d740e9b, the `andn` instruction
was implemented via `tcg_gen_andc` but passes the operands in the wrong
order:
- X86 defines `andn dest,src1,src2` as: dest = ~src1 & src2
- TCG defines `andc dest,src1,src2` as: dest = src1 & ~src2
 
I have also attached a simple test which shows the issue:

> user@ubuntu:~/Software$ ./a.out 
> 0000F000
> user@ubuntu:~/Software$ qemu/x86_64-linux-user/qemu-x86_64 -cpu max a.out 
> 0000000F

This patch fixes the problem by simply swapping the order of the two last
arguments in `tcg_gen_andc_tl`.

Signed-off-by: Alexandro Sanchez Bach <alexandro@phi.nz>
Cc: qemu-stable@nongnu.org
Reported-by: Alexandro Sanchez Bach <alexandro@phi.nz>
diff --git a/target/i386/translate.c b/target/i386/translate.c
index 0135415d92..3b7ce9232e 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -3802,7 +3802,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s,
int b,
                 }
                 ot = mo_64_32(s->dflag);
                 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
-                tcg_gen_andc_tl(cpu_T0, cpu_regs[s->vex_v], cpu_T0);
+                tcg_gen_andc_tl(cpu_T0, cpu_T0, cpu_regs[s->vex_v]);
                 gen_op_mov_reg_v(ot, reg, cpu_T0);
                 gen_op_update1_cc();
                 set_cc_op(s, CC_OP_LOGICB + ot);


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#include <stdio.h>=0A=
#include <stdint.h>=0A=
 =0A=
int main(void) {=0A=
    uint32_t ret =3D 0;=0A=
    __asm (=0A=
        "mov $0xFF00, %%ecx\n"=0A=
        "mov $0x0F0F, %%eax\n"=0A=
        "andn %%ecx, %%eax, %%ecx\n"=0A=
        "mov %%ecx, %0\n"=0A=
      : "=3Dr" (ret));=0A=
    printf("%08X\n", ret);=0A=
    return 0;=0A=
}=0A=
=0A=

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