From: Wei Wang2 Subject: [PATCH 2/3] AMD IOMMU: Propagate HyperTransport settings from IVHD table to control register Date: Wed, 3 Dec 2008 16:18:32 +0100 Message-ID: <1228317513.20236.301.camel@gran.amd.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="=-zWXKUopa/up4PDWBT0Rr" Return-path: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: xen-devel Cc: Keir Fraser List-Id: xen-devel@lists.xenproject.org --=-zWXKUopa/up4PDWBT0Rr Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Attached patch propagate HyperTransport settings suggested by IVHD table to iommu control register(MMIO offset 0018h).=20 -Wei Signed-off-by: Wei Wang -- AMD Saxony, Dresden, Germany Operating System Research Center Legal Information: AMD Saxony Limited Liability Company & Co. KG Sitz (Gesch=C3=A4ftsanschrift): Wilschdorfer Landstr. 101, 01109 Dresden, Deutschland Registergericht Dresden: HRA 4896 vertretungsberechtigter Komplement=C3=A4r: AMD Saxony LLC (Sitz Wilmington, Delaware, USA) Gesch=C3=A4ftsf=C3=BChrer der AMD Saxony LLC: Dr. Hans-R. Deppe, Thomas McCoy --=-zWXKUopa/up4PDWBT0Rr Content-Disposition: attachment; filename="ht.patch" Content-Type: text/x-patch; name="ht.patch"; charset="UTF-8" Content-Transfer-Encoding: 7bit diff -r ab0c1bdede53 xen/drivers/passthrough/amd/iommu_init.c --- a/xen/drivers/passthrough/amd/iommu_init.c Wed Nov 26 11:14:26 2008 +0000 +++ b/xen/drivers/passthrough/amd/iommu_init.c Wed Dec 03 13:32:42 2008 +0100 @@ -152,13 +152,33 @@ static void __init set_iommu_translation { u32 entry; - entry = readl(iommu->mmio_base+IOMMU_CONTROL_MMIO_OFFSET); - set_field_in_reg_u32(iommu->ht_tunnel_support ? IOMMU_CONTROL_ENABLED : - IOMMU_CONTROL_ENABLED, entry, + entry = readl(iommu->mmio_base + IOMMU_CONTROL_MMIO_OFFSET); + + if ( enable ) + { + set_field_in_reg_u32(iommu->ht_tunnel_support ? IOMMU_CONTROL_ENABLED : + IOMMU_CONTROL_DISABLED, entry, IOMMU_CONTROL_HT_TUNNEL_TRANSLATION_MASK, IOMMU_CONTROL_HT_TUNNEL_TRANSLATION_SHIFT, &entry); + set_field_in_reg_u32(iommu->isochronous ? IOMMU_CONTROL_ENABLED : + IOMMU_CONTROL_DISABLED, entry, + IOMMU_CONTROL_ISOCHRONOUS_MASK, + IOMMU_CONTROL_ISOCHRONOUS_SHIFT, &entry); + set_field_in_reg_u32(iommu->coherent ? IOMMU_CONTROL_ENABLED : + IOMMU_CONTROL_DISABLED, entry, + IOMMU_CONTROL_COHERENT_MASK, + IOMMU_CONTROL_COHERENT_SHIFT, &entry); + set_field_in_reg_u32(iommu->res_pass_pw ? IOMMU_CONTROL_ENABLED : + IOMMU_CONTROL_DISABLED, entry, + IOMMU_CONTROL_RESP_PASS_POSTED_WRITE_MASK, + IOMMU_CONTROL_RESP_PASS_POSTED_WRITE_SHIFT, &entry); + /* do not set PassPW bit */ + set_field_in_reg_u32(IOMMU_CONTROL_DISABLED, entry, + IOMMU_CONTROL_PASS_POSTED_WRITE_MASK, + IOMMU_CONTROL_PASS_POSTED_WRITE_SHIFT, &entry); + } set_field_in_reg_u32(enable ? IOMMU_CONTROL_ENABLED : - IOMMU_CONTROL_ENABLED, entry, + IOMMU_CONTROL_DISABLED, entry, IOMMU_CONTROL_TRANSLATION_ENABLE_MASK, IOMMU_CONTROL_TRANSLATION_ENABLE_SHIFT, &entry); writel(entry, iommu->mmio_base+IOMMU_CONTROL_MMIO_OFFSET); @@ -171,7 +191,7 @@ static void __init set_iommu_command_buf entry = readl(iommu->mmio_base+IOMMU_CONTROL_MMIO_OFFSET); set_field_in_reg_u32(enable ? IOMMU_CONTROL_ENABLED : - IOMMU_CONTROL_ENABLED, entry, + IOMMU_CONTROL_DISABLED, entry, IOMMU_CONTROL_COMMAND_BUFFER_ENABLE_MASK, IOMMU_CONTROL_COMMAND_BUFFER_ENABLE_SHIFT, &entry); writel(entry, iommu->mmio_base+IOMMU_CONTROL_MMIO_OFFSET); --=-zWXKUopa/up4PDWBT0Rr Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel --=-zWXKUopa/up4PDWBT0Rr--