From: Kumar Gala Date: Wed, 7 Apr 2010 12:34:30 -0500 Subject: [U-Boot] [PATCH] fsl-ddr: add the macro for Rtt_Nom definition In-Reply-To: <1270661671-28405-3-git-send-email-galak@kernel.crashing.org> References: <1270661671-28405-1-git-send-email-galak@kernel.crashing.org> <1270661671-28405-2-git-send-email-galak@kernel.crashing.org> <1270661671-28405-3-git-send-email-galak@kernel.crashing.org> Message-ID: <1270661671-28405-4-git-send-email-galak@kernel.crashing.org> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: Dave Liu add the macro definition for Rtt_Nom termination value for DDR3 Signed-off-by: Dave Liu --- include/asm-ppc/fsl_ddr_sdram.h | 8 +++++++- 1 files changed, 7 insertions(+), 1 deletions(-) diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/include/asm-ppc/fsl_ddr_sdram.h index 3216a50..02920db 100644 --- a/include/asm-ppc/fsl_ddr_sdram.h +++ b/include/asm-ppc/fsl_ddr_sdram.h @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Freescale Semiconductor, Inc. + * Copyright 2008-2010 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -24,6 +24,12 @@ #define DDR_OTF 6 /* on-the-fly BC4 and BL8 */ #define DDR_BL8 8 /* burst length 8 */ +#define DDR3_RTT_60_OHM 1 /* RTT_Nom = RZQ/4 */ +#define DDR3_RTT_120_OHM 2 /* RTT_Nom = RZQ/2 */ +#define DDR3_RTT_40_OHM 3 /* RTT_Nom = RZQ/6 */ +#define DDR3_RTT_20_OHM 4 /* RTT_Nom = RZQ/12 */ +#define DDR3_RTT_30_OHM 5 /* RTT_Nom = RZQ/8 */ + #if defined(CONFIG_FSL_DDR1) #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1) typedef ddr1_spd_eeprom_t generic_spd_eeprom_t; -- 1.6.0.6