From: Kumar Gala Date: Wed, 7 Apr 2010 12:34:31 -0500 Subject: [U-Boot] [PATCH] fsl-ddr: Add extra cycle to turnaround times In-Reply-To: <1270661671-28405-4-git-send-email-galak@kernel.crashing.org> References: <1270661671-28405-1-git-send-email-galak@kernel.crashing.org> <1270661671-28405-2-git-send-email-galak@kernel.crashing.org> <1270661671-28405-3-git-send-email-galak@kernel.crashing.org> <1270661671-28405-4-git-send-email-galak@kernel.crashing.org> Message-ID: <1270661671-28405-5-git-send-email-galak@kernel.crashing.org> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: Dave Liu Add an extra cycle turnaround time to read->write to ensure stability at high DDR frequencies. Signed-off-by: Dave Liu --- cpu/mpc8xxx/ddr/ctrl_regs.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index 03f9c43..4a282bc 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -198,6 +198,8 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr) pre_pd_exit_mclk = act_pd_exit_mclk; taxpd_mclk = 8; tmrd_mclk = 4; + /* set the turnaround time */ + trwt_mclk = 1; #else /* CONFIG_FSL_DDR2 */ /* * (tXARD and tXARDS). Empirical? -- 1.6.0.6