From: Sergio Monteiro Basto Subject: Re: [PATCH] drm/i915: be sure panel is powered up in eDP configs Date: Thu, 22 Jul 2010 04:09:31 +0100 Message-ID: <1279768171.21729.9.camel@segulix> References: <20100714154056.208b30c9@virtuousgeek.org> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0295804738==" Return-path: Received: from relay2.ptmail.sapo.pt (relay2.ptmail.sapo.pt [212.55.154.22]) by gabe.freedesktop.org (Postfix) with SMTP id 492059E76B for ; Wed, 21 Jul 2010 20:15:59 -0700 (PDT) Received: from unknown (HELO sergiomb.no-ip.org) (sergiomb@sapo.pt@[2.81.192.80]) (envelope-sender ) by mta12 (qmail-ldap-1.03) with AES256-SHA encrypted SMTP for ; 22 Jul 2010 03:09:19 -0000 In-Reply-To: <20100714154056.208b30c9@virtuousgeek.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jesse Barnes Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============0295804738== Content-Type: multipart/signed; micalg="sha1"; protocol="application/x-pkcs7-signature"; boundary="=-VcPy6cBVwaxfwPSsVXZv" --=-VcPy6cBVwaxfwPSsVXZv Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi!,=20 so what is the state of this ? From: Adam Jackson To: intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] [PATCH 1/6] drm/i915/dp: Rename has_edp to is_pch_edp to reflect its real meaning Date: Fri, 16 Jul 2010 14:46:27 -0400 (07/16/2010 07:46:27 PM) seems that have something related to this. Should I try yours patch in this email ?=20 On Wed, 2010-07-14 at 15:40 -0700, Jesse Barnes wrote:=20 > Fixes https://bugs.freedesktop.org/show_bug.cgi?id=3D28739. We need to > enable power to the panel with the AUX VDD bit in order to properly > detect the eDP attached panel, and we also need to turn the panel on in > case it was off when we started (as happens at resume time). >=20 > But this patch raises a couple of questions: > 1) why does the first panel on sequence time out? > 2) why do I need to unlock the panel protected regs? >=20 > Keith, I think this is your code, any ideas? >=20 > Thanks, > Jesse >=20 > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index 42c6024..b191f02 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -2805,6 +2805,7 @@ > =20 > #define PCH_PP_STATUS 0xc7200 > #define PCH_PP_CONTROL 0xc7204 > +#define PANEL_UNLOCK_REGS (0xabcd << 16) > #define EDP_FORCE_VDD (1 << 3) > #define EDP_BLC_ENABLE (1 << 2) > #define PANEL_POWER_RESET (1 << 1) > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel= _dp.c > index b4f0282..a20dd7b 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -744,6 +744,32 @@ intel_dp_mode_set(struct drm_encoder *encoder, struc= t drm_display_mode *mode, > } > } > =20 > +static void ironlake_edp_panel_on(struct drm_device *dev) > +{ > + struct drm_i915_private *dev_priv =3D dev->dev_private; > + unsigned long timeout =3D jiffies + msecs_to_jiffies(5000); > + u32 pp, pp_status; > + > + pp_status =3D I915_READ(PCH_PP_STATUS); > + if (pp_status & PP_ON) > + return; > + > + DRM_DEBUG_KMS("\n"); > + pp =3D I915_READ(PCH_PP_CONTROL); > + pp |=3D POWER_TARGET_ON; > + I915_WRITE(PCH_PP_CONTROL, pp); > + do { > + pp_status =3D I915_READ(PCH_PP_STATUS); > + } while (((pp_status & PP_ON) =3D=3D 0) && !time_after(jiffies, timeout= )); > + > + if (time_after(jiffies, timeout)) > + DRM_DEBUG_KMS("panel on wait timed out: 0x%08x\n", pp_status); > + > + pp |=3D PANEL_UNLOCK_REGS; > + pp &=3D ~EDP_FORCE_VDD; > + I915_WRITE(PCH_PP_CONTROL, pp); > +} > + > static void ironlake_edp_backlight_on (struct drm_device *dev) > { > struct drm_i915_private *dev_priv =3D dev->dev_private; > @@ -755,6 +781,28 @@ static void ironlake_edp_backlight_on (struct drm_de= vice *dev) > I915_WRITE(PCH_PP_CONTROL, pp); > } > =20 > +static void ironlake_edp_panel_off(struct drm_device *dev) > +{ > + struct drm_i915_private *dev_priv =3D dev->dev_private; > + unsigned long timeout =3D jiffies + msecs_to_jiffies(5000); > + u32 pp, pp_status; > + > + DRM_DEBUG_KMS("\n"); > + pp =3D I915_READ(PCH_PP_CONTROL); > + pp &=3D ~POWER_TARGET_ON; > + I915_WRITE(PCH_PP_CONTROL, pp); > + do { > + pp_status =3D I915_READ(PCH_PP_STATUS); > + } while ((pp_status & PP_ON) && !time_after(jiffies, timeout)); > + > + if (time_after(jiffies, timeout)) > + DRM_DEBUG_KMS("panel off wait timed out\n"); > + > + /* Make sure VDD is enabled so DP AUX will work */ > + pp |=3D EDP_FORCE_VDD; > + I915_WRITE(PCH_PP_CONTROL, pp); > +} > + > static void ironlake_edp_backlight_off (struct drm_device *dev) > { > struct drm_i915_private *dev_priv =3D dev->dev_private; > @@ -776,16 +824,24 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode= ) > uint32_t dp_reg =3D I915_READ(dp_priv->output_reg); > =20 > if (mode !=3D DRM_MODE_DPMS_ON) { > + if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) { > + ironlake_edp_backlight_off(dev); > + ironlake_edp_panel_off(dev); > + } > if (dp_reg & DP_PORT_EN) { > intel_dp_link_down(intel_encoder, dp_priv->DP); > - if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) > - ironlake_edp_backlight_off(dev); > } > } else { > + /* Turn off the panel so we can modify DP_A etc */ > + if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) > + ironlake_edp_panel_off(dev); > if (!(dp_reg & DP_PORT_EN)) { > intel_dp_link_train(intel_encoder, dp_priv->DP, dp_priv->link_configu= ration); > - if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) > - ironlake_edp_backlight_on(dev); > + } > + if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) { > + if (I915_READ(dp_priv->output_reg) & DP_PORT_EN) > + ironlake_edp_panel_on(dev); > + ironlake_edp_backlight_on(dev); > } > } > dp_priv->dpms_mode =3D mode; > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx --=20 S=C3=A9rgio M. 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