Received: from eggs.gnu.org ([2001:4830:134:3::10]:58823) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V9U61-0000iy-FF for qemu-devel@nongnu.org; Wed, 14 Aug 2013 01:58:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V9U5t-0003Er-0x for qemu-devel@nongnu.org; Wed, 14 Aug 2013 01:58:13 -0400 Received: from mail-qc0-x230.google.com ([2607:f8b0:400d:c01::230]:32834) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V9U5s-0003Ej-U8 for qemu-devel@nongnu.org; Wed, 14 Aug 2013 01:58:04 -0400 Received: by mail-qc0-f176.google.com with SMTP id u12so4624702qcx.35 for ; Tue, 13 Aug 2013 22:58:04 -0700 (PDT) From: Xi Wang Date: Wed, 14 Aug 2013 01:55:28 -0400 Message-Id: <1376459728-2029-2-git-send-email-xi.wang@gmail.com> In-Reply-To: <1376459728-2029-1-git-send-email-xi.wang@gmail.com> References: <1376459728-2029-1-git-send-email-xi.wang@gmail.com> Subject: [Qemu-devel] [PATCH v2 2/2] hw/openrisc: avoid undefined shift in openrisc_pic_cpu_handler() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Jia Liu , Xi Wang In C99 signed shift (1 << 31) is undefined behavior, since the result exceeds INT_MAX. Use 1U instead and move the shift after the check. Cc: Jia Liu Cc: Paolo Bonzini Signed-off-by: Xi Wang --- hw/openrisc/pic_cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/openrisc/pic_cpu.c b/hw/openrisc/pic_cpu.c index 3fcee02..2af1d60 100644 --- a/hw/openrisc/pic_cpu.c +++ b/hw/openrisc/pic_cpu.c @@ -26,12 +26,14 @@ static void openrisc_pic_cpu_handler(void *opaque, int irq, int level) { OpenRISCCPU *cpu = (OpenRISCCPU *)opaque; CPUState *cs = CPU(cpu); - uint32_t irq_bit = 1 << irq; + uint32_t irq_bit; if (irq > 31 || irq < 0) { return; } + irq_bit = 1U << irq; + if (level) { cpu->env.picsr |= irq_bit; } else { -- 1.8.1.2