From: Paulo Zanoni Subject: [PATCH 1/2] drm/i915: move HSW DDI pll enabling to haswell_crtc_enable Date: Fri, 23 May 2014 11:51:24 -0300 Message-ID: <1400856685-3158-2-git-send-email-przanoni@gmail.com> References: <1400856685-3158-1-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-yh0-f42.google.com (mail-yh0-f42.google.com [209.85.213.42]) by gabe.freedesktop.org (Postfix) with ESMTP id 8E9656E5B5 for ; Fri, 23 May 2014 07:51:44 -0700 (PDT) Received: by mail-yh0-f42.google.com with SMTP id t59so4295879yho.15 for ; Fri, 23 May 2014 07:51:44 -0700 (PDT) In-Reply-To: <1400856685-3158-1-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: intel-gfx@lists.freedesktop.org Cc: Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org From: Paulo Zanoni Now that we moved all the register writing to haswell_crtc_enable, we can also move the PLL enabling there. This is the last step to do before allowing runtime PM on DPMS. Daniel has some patches to do this while also moving all the HSW PLL code to the shared DPLL structs, but while we still discuss the color of those patches, we can apply this quick one and at least get runtime PM on DPMS running in the meantime. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_display.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 3da73ef..1ea4fbe 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4052,6 +4052,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) if (intel_crtc->active) return; + intel_ddi_pll_enable(intel_crtc); + if (intel_crtc->config.has_dp_encoder) intel_dp_set_m_n(intel_crtc); @@ -4243,6 +4245,8 @@ static void haswell_crtc_disable(struct drm_crtc *crtc) intel_update_fbc(dev); intel_edp_psr_update(dev); mutex_unlock(&dev->struct_mutex); + + intel_ddi_put_crtc_pll(crtc); } static void ironlake_crtc_off(struct drm_crtc *crtc) @@ -4253,7 +4257,6 @@ static void ironlake_crtc_off(struct drm_crtc *crtc) static void haswell_crtc_off(struct drm_crtc *crtc) { - intel_ddi_put_crtc_pll(crtc); } static void i9xx_pfit_enable(struct intel_crtc *crtc) @@ -7471,7 +7474,6 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc, if (!intel_ddi_pll_select(intel_crtc)) return -EINVAL; - intel_ddi_pll_enable(intel_crtc); intel_crtc->lowfreq_avail = false; -- 1.9.0