From: Joakim Tjernlund <Joakim.Tjernlund@infinera.com>
Date: Tue, 29 Aug 2017 13:21:22 +0000
Subject: [U-Boot] setup of PEX_GCLK_RATIO in E500 CPUs(P2010) missing ?
In-Reply-To: <1504003621.4350.49.camel@infinera.com>
References: <1504003621.4350.49.camel@infinera.com>
Message-ID: <1504012881.32677.3.camel@infinera.com>
List-Id: <u-boot.lists.denx.de>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
To: u-boot@lists.denx.de

On Tue, 2017-08-29 at 12:47 +0200, Joakim Tjernlund wrote:
> As we are looking at PCI stuff ATM I would like to ask
> about PEX_GCLK_RATIO in E500 CPUs. I cannot find this is setup
> at all for E500 but I THINK this is required.
> 
> In 83xx one do:
> get_clocks();
> /* Configure the PCIE controller core clock ratio */
> out_le32(hose_cfg_base + PEX_GCLK_RATIO,

A bit strange with out_le32 instead of out_be32 ?

> (((bus ? gd->arch.pciexp2_clk : gd->arch.pciexp1_clk)
> / 1000000) * 16) / 333);
> udelay(1000000);
> 
> Any clues?
> 
>  Jocke
Seems like only 83xx is setting this parameter.

Anyhow, I put together this patch:

--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -322,6 +322,10 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
 
        pci_setup_indirect(hose, cfg_addr, cfg_data);
 
+       /* Configure the PCIE controller core clock ratio */
+       pci_hose_write_config_dword(hose, dev, 0x440, (gd->bus_clk / 333333333) * 16);
+       /* udelay(1000000) needed here ?*/
+
        block_rev = in_be32(&pci->block_rev1);
        if (PEX_IP_BLK_REV_2_2 <= block_rev) {
                pi = &pci->pit[2];      /* 0xDC0 */

Any chance this will work for all supported FSL PCIe controllers?

 Jocke