From: Rex Zhu Subject: [PATCH 4/4] drm/amd/powerplay: fix pcie max lane define error Date: Wed, 13 Sep 2017 21:08:36 +0800 Message-ID: <1505308116-31991-4-git-send-email-Rex.Zhu@amd.com> References: <1505308116-31991-1-git-send-email-Rex.Zhu@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1505308116-31991-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org> List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Cc: Rex Zhu Q2hhbmdlLUlkOiBJMzA3NDY1ZWMyZmU4ZmUwMmUxOWM3NmQ5NzliZTBhMWFmMzBmZWQwYwpTaWdu ZWQtb2ZmLWJ5OiBSZXggWmh1IDxSZXguWmh1QGFtZC5jb20+Ci0tLQogZHJpdmVycy9ncHUvZHJt L2FtZC9wb3dlcnBsYXkvaW5jL2hhcmR3YXJlbWFuYWdlci5oIHwgMiArLQogMSBmaWxlIGNoYW5n ZWQsIDEgaW5zZXJ0aW9uKCspLCAxIGRlbGV0aW9uKC0pCgpkaWZmIC0tZ2l0IGEvZHJpdmVycy9n cHUvZHJtL2FtZC9wb3dlcnBsYXkvaW5jL2hhcmR3YXJlbWFuYWdlci5oIGIvZHJpdmVycy9ncHUv ZHJtL2FtZC9wb3dlcnBsYXkvaW5jL2hhcmR3YXJlbWFuYWdlci5oCmluZGV4IDYyOTk5MGYuLjU3 YTA0NjcgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1L2RybS9hbWQvcG93ZXJwbGF5L2luYy9oYXJk d2FyZW1hbmFnZXIuaAorKysgYi9kcml2ZXJzL2dwdS9kcm0vYW1kL3Bvd2VycGxheS9pbmMvaGFy ZHdhcmVtYW5hZ2VyLmgKQEAgLTI5Nyw3ICsyOTcsNyBAQCBlbnVtIFBQX1BDSUVHZW4gewogI2Rl ZmluZSBQUF9NaW5fUENJRUdlbiAgICAgUFBfUENJRUdlbjEKICNkZWZpbmUgUFBfTWF4X1BDSUVH ZW4gICAgIFBQX1BDSUVHZW4zCiAjZGVmaW5lIFBQX01pbl9QQ0lFTGFuZSAgICAxCi0jZGVmaW5l IFBQX01heF9QQ0lFTGFuZSAgICAzMgorI2RlZmluZSBQUF9NYXhfUENJRUxhbmUgICAgMTYKIAog ZW51bSBwaG1fY2xvY2tfVHlwZSB7CiAJUEhNX0Rpc3BDbG9jayA9IDEsCi0tIAoxLjkuMQoKX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KYW1kLWdmeCBtYWls aW5nIGxpc3QKYW1kLWdmeEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVl ZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9hbWQtZ2Z4Cg==