From: Manu Gautam Subject: [PATCH v5 06/17] phy: qcom-qmp: Move SERDES/PCS START after PHY reset Date: Tue, 16 Jan 2018 16:27:01 +0530 Message-ID: <1516100232-18623-7-git-send-email-mgautam@codeaurora.org> References: <1516100232-18623-1-git-send-email-mgautam@codeaurora.org> Return-path: In-Reply-To: <1516100232-18623-1-git-send-email-mgautam@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org To: Kishon Vijay Abraham I Cc: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, Manu Gautam , Vivek Gautam , Varadarajan Narayanan , Jaehoon Chung , Fengguang Wu , Wei Yongjun , "open list:GENERIC PHY FRAMEWORK" List-Id: linux-arm-msm@vger.kernel.org Driver is currently performing PHY reset after starting SERDES/PCS. As per hardware datasheet reset must be done before starting PHY. Hence, update the sequence. Signed-off-by: Manu Gautam --- drivers/phy/qualcomm/phy-qcom-qmp.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index ecff261..edb6bbe 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -896,12 +896,12 @@ static int qcom_qmp_phy_init(struct phy *phy) if (cfg->has_pwrdn_delay) usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); - /* start SerDes and Phy-Coding-Sublayer */ - qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); - /* Pull PHY out of reset state */ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + /* start SerDes and Phy-Coding-Sublayer */ + qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); + status = pcs + cfg->regs[QPHY_PCS_READY_STATUS]; mask = cfg->mask_pcs_ready; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project