From: Ilia Lin Subject: [PATCH] dt: qcom: Fix SPI5 config on MSM8996 Date: Tue, 23 Jan 2018 09:36:18 +0200 Message-ID: <1516692978-5453-1-git-send-email-ilialin@codeaurora.org> Return-path: Received: from smtp.codeaurora.org ([198.145.29.96]:46570 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750907AbeAWHgW (ORCPT ); Tue, 23 Jan 2018 02:36:22 -0500 Sender: linux-arm-msm-owner@vger.kernel.org List-Id: linux-arm-msm@vger.kernel.org To: linux-arm-msm@vger.kernel.org Cc: andy.gross@linaro.org, celster@codeaurora.org, tfinkel@codeaurora.org, nicolas.dechesne@linaro.org, srinivas.kandagatla@linaro.org Set correct clocks and interrupt values. Fixes the incorrect SPI master configuration. This is mandatory to make the SPI5 interface functional. Signed-off-by: Ilia Lin --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 511b7bd..98a8608e 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -770,8 +770,8 @@ blsp2_spi5: spi@075ba000{ compatible = "qcom,spi-qup-v2.2.1"; reg = <0x075ba000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>, + interrupts = ; + clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; clock-names = "core", "iface"; pinctrl-names = "default", "sleep"; -- 1.9.1