From: Bin Meng Date: Tue, 13 Nov 2018 00:22:03 -0800 Subject: [U-Boot] [PATCH 15/19] riscv: Return to previous privilege level after trap handling In-Reply-To: <1542097327-6629-1-git-send-email-bmeng.cn@gmail.com> References: <1542097327-6629-1-git-send-email-bmeng.cn@gmail.com> Message-ID: <1542097327-6629-16-git-send-email-bmeng.cn@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de At present the trap handler returns to M-mode only. Change to returning to previous privilege level instead. Signed-off-by: Bin Meng --- arch/riscv/cpu/mtrap.S | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/riscv/cpu/mtrap.S b/arch/riscv/cpu/mtrap.S index 6c0eac6..c9010c7 100644 --- a/arch/riscv/cpu/mtrap.S +++ b/arch/riscv/cpu/mtrap.S @@ -68,9 +68,6 @@ trap_entry: jal handle_trap csrw mepc, a0 - /* Remain in M-mode after mret */ - li t0, MSTATUS_MPP - csrs mstatus, t0 LREG x1, 1 * REGBYTES(sp) LREG x3, 3 * REGBYTES(sp) LREG x4, 4 * REGBYTES(sp) -- 2.7.4