From: Bin Meng Date: Tue, 13 Nov 2018 00:22:05 -0800 Subject: [U-Boot] [PATCH 17/19] riscv: Pass correct exception code to _exit_trap() In-Reply-To: <1542097327-6629-1-git-send-email-bmeng.cn@gmail.com> References: <1542097327-6629-1-git-send-email-bmeng.cn@gmail.com> Message-ID: <1542097327-6629-18-git-send-email-bmeng.cn@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de The most significant bit in mcause register should be masked to form the exception code for _exit_trap(). Signed-off-by: Bin Meng --- arch/riscv/lib/interrupts.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index c568706..5e09196 100644 --- a/arch/riscv/lib/interrupts.c +++ b/arch/riscv/lib/interrupts.c @@ -73,7 +73,7 @@ ulong handle_trap(ulong mcause, ulong epc, struct pt_regs *regs) else if ((is_int) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)) timer_interrupt(0); /* handle_m_timer_interrupt */ else - _exit_trap(mcause, epc, regs); + _exit_trap(mcause & MCAUSE_CAUSE, epc, regs); return epc; } -- 2.7.4