Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1HNWUL-0004c2-B1 for qemu-devel@nongnu.org; Sat, 03 Mar 2007 10:49:37 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1HNWUJ-0004ak-K2 for qemu-devel@nongnu.org; Sat, 03 Mar 2007 10:49:36 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1HNWUI-0004a2-Ir for qemu-devel@nongnu.org; Sat, 03 Mar 2007 10:49:34 -0500 Received: from vc4-2-0-87.dsl.netrack.net ([199.45.160.85] helo=harmony.bsdimp.com) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA:32) (Exim 4.52) id 1HNWUH-0004IJ-RY for qemu-devel@nongnu.org; Sat, 03 Mar 2007 10:49:34 -0500 Date: Sat, 03 Mar 2007 08:47:18 -0700 (MST) Message-Id: <20070303.084718.1723235906.imp@bsdimp.com> Subject: Re: [Qemu-devel] [PATCH] pcnet32 driver change, please test From: "M. Warner Losh" In-Reply-To: References: <20070303.062452.129711022.imp@bsdimp.com> Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: schwab@suse.de Cc: qemu-devel@nongnu.org In message: Andreas Schwab writes: : "M. Warner Losh" writes: : : > Except that compilers use the convention that was described above. : > Big endian MIPS definitely uses a different bit ordering for C bit : > fields than little endian MIPS. : : There is actually a difference between *bitfield* ordering and *bit* : ordering. The former always follows the byte ordering, whereas the latter : is only a property of the ISA and has no influence on the ABI or API. True, but that's not what the original poster in this thread was asking. Answering the different question is just confusing to the original poster. Warner