From: "Christoph Egger" Subject: [PATCH] [HVM][SVM] Handle threshold register for guests Date: Mon, 21 May 2007 19:24:55 +0200 Message-ID: <200705211924.55185.Christoph.Egger@amd.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="Boundary-00=_nXdUGibqT8zphIZ" Return-path: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: xen-devel@lists.xensource.com List-Id: xen-devel@lists.xenproject.org --Boundary-00=_nXdUGibqT8zphIZ Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Hi! The threshold register has been introduced in AMD RevF CPUs along with SVM (Actually this MCA/MCE msr register existed before, but had no meaning). Therefore no need for additional cpuid checks. On read access it reports the HVM guest the register has been locked by the= =20 BIOS. This means, it is not available for OS use. Thus, write accesses are simply ignored. This behaviour actually matches real HW, so guests can deal with this. =46urther, this way no multiplexing for multiple guests is necessary. Please apply. Signed off by: Christoph Egger =2D-=20 AMD Saxony, Dresden Germany Operating System Research Center Legal Information: AMD Saxony Limited Liability Company & Co. KG Sitz (Gesch=E4ftsanschrift): Wilschdorfer Landstr. 101, 01109 Dresden, Deutschland Registergericht Dresden: HRA 4896 vertretungsberechtigter Komplement=E4r: AMD Saxony LLC (Sitz Wilmington, Delaware, USA) Gesch=E4ftsf=FChrer der AMD Saxony LLC: Dr. Hans-R. Deppe, Thomas McCoy --Boundary-00=_nXdUGibqT8zphIZ Content-Type: text/x-diff; charset=iso-8859-1; name=xen_threshold.diff Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename=xen_threshold.diff diff -r 089696e0c603 xen/arch/x86/hvm/svm/svm.c --- a/xen/arch/x86/hvm/svm/svm.c Thu May 17 11:42:46 2007 +0100 +++ b/xen/arch/x86/hvm/svm/svm.c Mon May 21 19:09:59 2007 +0200 @@ -177,6 +177,14 @@ static inline int long_mode_do_msr_write if ( !svm_paging_enabled(v) ) vmcb->efer &= ~(EFER_LME | EFER_LMA); + break; + + case MSR_K8_MC4_MISC: /* Threshold register */ + /* MCA/MCE: Threshold register is reported to be locked. + * So we ignore all write accesses. This behaviour + * matches real HW, so guests should have no problem + * with this. + */ break; default: @@ -2062,6 +2070,14 @@ static inline void svm_do_msr_access( msr_content = v->arch.hvm_svm.cpu_shadow_efer; break; + case MSR_K8_MC4_MISC: /* Threshold register */ + /* MCA/MCE: We report HVM guests, threshold register + * is not available for OS use. The value means, + * the msr has been locked by the BIOS. + */ + msr_content = 0x2000000000000000ULL; + break; + default: if ( rdmsr_hypervisor_regs(ecx, &eax, &edx) || rdmsr_safe(ecx, eax, edx) == 0 ) diff -r 089696e0c603 xen/include/asm-x86/msr.h --- a/xen/include/asm-x86/msr.h Thu May 17 11:42:46 2007 +0100 +++ b/xen/include/asm-x86/msr.h Mon May 21 19:08:35 2007 +0200 @@ -216,6 +216,28 @@ static inline void write_efer(__u64 val) #define MSR_IA32_MC0_STATUS 0x401 #define MSR_IA32_MC0_ADDR 0x402 #define MSR_IA32_MC0_MISC 0x403 + +/* K8 MC MSR */ +#define MSR_K8_MC1_CTL 0x404 +#define MSR_K8_MC1_STATUS 0x405 +#define MSR_K8_MC1_ADDR 0x406 +#define MSR_K8_MC1_MISC 0x407 + +#define MSR_K8_MC2_CTL 0x408 +#define MSR_K8_MC2_STATUS 0x409 +#define MSR_K8_MC2_ADDR 0x40A +#define MSR_K8_MC2_MISC 0x40B + +#define MSR_K8_MC3_CTL 0x40C +#define MSR_K8_MC3_STATUS 0x40D +#define MSR_K8_MC3_ADDR 0x40E +#define MSR_K8_MC3_MISC 0x40F + +#define MSR_K8_MC4_CTL 0x410 +#define MSR_K8_MC4_STATUS 0x411 +#define MSR_K8_MC4_ADDR 0x412 +#define MSR_K8_MC4_MISC 0x413 + /* Pentium IV performance counter MSRs */ #define MSR_P4_BPU_PERFCTR0 0x300 --Boundary-00=_nXdUGibqT8zphIZ Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel --Boundary-00=_nXdUGibqT8zphIZ--