Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1IFGhj-000784-F8 for qemu-devel@nongnu.org; Sun, 29 Jul 2007 17:53:35 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1IFGhi-00077S-Ug for qemu-devel@nongnu.org; Sun, 29 Jul 2007 17:53:35 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1IFGhi-00077E-S0 for qemu-devel@nongnu.org; Sun, 29 Jul 2007 17:53:34 -0400 Received: from hall.aurel32.net ([88.191.38.19]) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1IFGhi-0006ds-BM for qemu-devel@nongnu.org; Sun, 29 Jul 2007 17:53:34 -0400 Received: from aurel32 by hall.aurel32.net with local (Exim 4.63) (envelope-from ) id 1IFGhd-0000JG-Tv for qemu-devel@nongnu.org; Sun, 29 Jul 2007 23:53:29 +0200 Date: Sun, 29 Jul 2007 23:53:29 +0200 From: Aurelien Jarno Message-ID: <20070729215329.GA820@hall.aurel32.net> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline Sender: "aurel32,,," Subject: [Qemu-devel] [PATCH, MIPS] Fix cache configuration of 5Kc, 5Kf and 20Kf CPU Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Hi all, There is currently a bug in the MIPS system emulation with the CP0 config 1 register. The default cache values are setting at the top of the file and the ored with other values below. While this works for boolean fields, in does not work for fields which hold a value. For example, the default value of CP0C1_IL is 3, and it is set later to 4 for the 5Kc, 5Kf and 20Kf processors. The result is not 4, but 7 which is a reserved value. This prevents 2.6.22 kernel from working on those processors. The patch below fixes that. Cheers, Aurelien Index: target-mips/translate_init.c =================================================================== RCS file: /sources/qemu/qemu/target-mips/translate_init.c,v retrieving revision 1.17 diff -u -d -p -r1.17 translate_init.c --- target-mips/translate_init.c 23 Jun 2007 18:04:12 -0000 1.17 +++ target-mips/translate_init.c 29 Jul 2007 21:47:00 -0000 @@ -28,15 +28,11 @@ (0x0 << CP0C0_AT) | (0x0 << CP0C0_AR) | (0x1 << CP0C0_MT) | \ (0x2 << CP0C0_K0)) -/* Have config2, 64 sets Icache, 16 bytes Icache line, - 2-way Icache, 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache, - no coprocessor2 attached, no MDMX support attached, +/* Have config2, no coprocessor2 attached, no MDMX support attached, no performance counters, watch registers present, no code compression, EJTAG present, no FPU */ #define MIPS_CONFIG1 \ ((1 << CP0C1_M) | \ - (0x0 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x1 << CP0C1_IA) | \ - (0x0 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x1 << CP0C1_DA) | \ (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \ (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \ (0 << CP0C1_FP)) @@ -82,7 +78,9 @@ static mips_def_t mips_defs[] = .name = "4Kc", .CP0_PRid = 0x00018000, .CP0_Config0 = MIPS_CONFIG0, - .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU), + .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), .CP0_Config2 = MIPS_CONFIG2, .CP0_Config3 = MIPS_CONFIG3, .SYNCI_Step = 32, @@ -94,7 +92,9 @@ static mips_def_t mips_defs[] = .name = "4KEcR1", .CP0_PRid = 0x00018400, .CP0_Config0 = MIPS_CONFIG0, - .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU), + .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), .CP0_Config2 = MIPS_CONFIG2, .CP0_Config3 = MIPS_CONFIG3, .SYNCI_Step = 32, @@ -106,7 +106,9 @@ static mips_def_t mips_defs[] = .name = "4KEc", .CP0_PRid = 0x00019000, .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR), - .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU), + .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), .CP0_Config2 = MIPS_CONFIG2, .CP0_Config3 = MIPS_CONFIG3, .SYNCI_Step = 32, @@ -118,7 +120,9 @@ static mips_def_t mips_defs[] = .name = "24Kc", .CP0_PRid = 0x00019300, .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR), - .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU), + .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), .CP0_Config2 = MIPS_CONFIG2, .CP0_Config3 = MIPS_CONFIG3, .SYNCI_Step = 32, @@ -130,7 +134,9 @@ static mips_def_t mips_defs[] = .name = "24Kf", .CP0_PRid = 0x00019300, .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR), - .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU), + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), .CP0_Config2 = MIPS_CONFIG2, .CP0_Config3 = MIPS_CONFIG3, .SYNCI_Step = 32, @@ -145,7 +151,9 @@ static mips_def_t mips_defs[] = .name = "R4000", .CP0_PRid = 0x00000400, .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT), - .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU), + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), .CP0_Config2 = MIPS_CONFIG2, .CP0_Config3 = MIPS_CONFIG3, .SYNCI_Step = 16, -- .''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' aurel32@debian.org | aurelien@aurel32.net `- people.debian.org/~aurel32 | www.aurel32.net