Date: Mon, 24 Sep 2007 13:50:50 +0100
From: Thiemo Seufer <ths@networkno.de>
Subject: Re: [Qemu-devel] [PATCH][MIPS] Per-CPU instruction decoding
	implementation
Message-ID: <20070924125046.GB27468@networkno.de>
References: <20070919214757.GA14637@hall.aurel32.net>
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In-Reply-To: <20070919214757.GA14637@hall.aurel32.net>
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To: Aurelien Jarno <aurelien@aurel32.net>
Cc: qemu-devel@nongnu.org

Aurelien Jarno wrote:
> Hi all,
> 
> The patch below implements per-cpu decoding on the MIPS target. The 
> supported instruction set is defined by a set of flags. It assumes that
> MIPS2 instructions are always supported. It also removes the check for 
> CP0C0_AT when setting MIPS_HFLAG_64 as it is now obsolete.

I expanded parts of it to (at least theoretically) cover the whole
ISA space, renamed INSN -> ISA / ASE, since that's what we actually
check for, and fixed a few misassumptions (e.g. Xcontext is MIPS3).


Thiemo