Date: Mon, 10 Dec 2007 10:13:18 +0100
From: Aurelien Jarno <aurelien@aurel32.net>
Message-ID: <20071210091318.GA3937@hall.aurel32.net>
MIME-Version: 1.0
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Sender: "aurel32,,," <aurel32@hall.aurel32.net>
Subject: [Qemu-devel] [PATCH][PPC] mtfsf: fix FPSCR_VX and FPSCR_FEX
	computation
Reply-To: qemu-devel@nongnu.org
To: qemu-devel@nongnu.org

Hi all,

The patch below fix the computation of FPSCR_VX and FPSCR_FEX when
using the mtfsf instruction. As stated in the PowerPC manual the mtfsf
instruction can't alter those bit, and thus it should always be 
computed.

Bye,
Aurelien

Index: target-ppc/op_helper.c
===================================================================
RCS file: /sources/qemu/qemu/target-ppc/op_helper.c,v
retrieving revision 1.73
diff -u -d -p -r1.73 op_helper.c
--- target-ppc/op_helper.c	24 Nov 2007 02:03:55 -0000	1.73
+++ target-ppc/op_helper.c	10 Dec 2007 09:10:30 -0000
@@ -888,12 +888,16 @@ void do_store_fpscr (uint32_t mask)
     /* Update VX and FEX */
     if (fpscr_ix != 0)
         env->fpscr |= 1 << FPSCR_VX;
+    else
+        env->fpscr &= ~(1 << FPSCR_VX);
     if ((fpscr_ex & fpscr_eex) != 0) {
         env->fpscr |= 1 << FPSCR_FEX;
         env->exception_index = POWERPC_EXCP_PROGRAM;
         /* XXX: we should compute it properly */
         env->error_code = POWERPC_EXCP_FP;
     }
+    else
+        env->fpscr &= ~(1 << FPSCR_FEX);
     fpscr_set_rounding_mode();
 }
 #undef WORD0

-- 
  .''`.  Aurelien Jarno	            | GPG: 1024D/F1BCDB73
 : :' :  Debian developer           | Electrical Engineer
 `. `'   aurel32@debian.org         | aurelien@aurel32.net
   `-    people.debian.org/~aurel32 | www.aurel32.net