From: Jean-Christophe PLAGNIOL-VILLARD Date: Sat, 22 Mar 2008 14:23:08 +0100 Subject: [U-Boot-Users] [PATCH] DM644x: (2nd try) This patch removes all board specific code from the arch. part for DM644x (DaVinci) boards In-Reply-To: <4CD35CD1F8085945B597F80EEC8942138A2497@exc01.bk.prodrive.nl> References: <4CD35CD1F8085945B597F80EEC8942138A2497@exc01.bk.prodrive.nl> Message-ID: <20080322132308.GA17673@game.jcrosoft.org> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 12:24 Fri 21 Mar , Pieter Voorthuijsen wrote: > Hello Jean-Christophe, > > Thanks for looking into the code, unfortunatly I cannot use the > git-send-email :( Outlook seems to only be able to wrap so I'll attach > the pacthes as a file... I double checked for spaces and coding style.. > >diff --git a/cpu/arm926ejs/davinci/lowlevel_init.S b/cpu/arm926ejs/davinci/lowlevel_init.S >index a87c112..9b03628 100644 2D >--- a/cpu/arm926ejs/davinci/lowlevel_init.S >+++ b/cpu/arm926ejs/davinci/lowlevel_init.S >@@ -3,6 +3,11 @@ > * > * Copyright (C) 2007 Sergey Kubushyn > * >+ * Copyright (C) 2008 Prodrive BV >+ * Changed: >+ * Made board specific defines such as DDR timing and PLL ^ Whitespace please remove >+ * dividers. These should be set in the board config file. >+ * > * Partially based on TI sources, original copyrights follow: > */ >diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h >index 8ecd059..f849be6 100644 >--- a/include/configs/davinci_dvevm.h >+++ b/include/configs/davinci_dvevm.h >@@ -52,6 +52,8 @@ > #define DV_EVM > #define CFG_NAND_SMALLPAGE > #define CFG_USE_NOR >+#define CFG_USE_INTEL_NOR /* Define this when your DVEVM has Intel ^ Whitespace please remove >+ * flash instead of AMD flash */ and please use this style of comment /* * Comment * Comment */ > /*===================*/ > /* SoC Configuration */ > /*===================*/ >@@ -60,6 +62,24 @@ > #define CFG_TIMERBASE 0x01c21400 /* use timer 0 */ > #define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */ > #define CFG_HZ 1000 >+#define CFG_DAVINCI_PINMUX_0 0x00000c1f >+#define CFG_DAVINCI_WAITCFG 0x00000000 >+#define CFG_DAVINCI_ACFG2 0x3ffffffd /* CE configs */ >+#define CFG_DAVINCI_ACFG3 0x3ffffffd >+#define CFG_DAVINCI_ACFG4 0x3ffffffd >+#define CFG_DAVINCI_ACFG5 0x3ffffffd >+#undef CFG_DAVINCI_NANDCE /* When using NAND, define 2,3 or 4 */ >+#define CFG_DAVINCI_DDRCTL 0x50006405 /* DDR timing config */ >+#define CFG_DAVINCI_SDREF 0x000005c3 >+#define CFG_DAVINCI_SDCFG 0x00178632 /* 8 banks */ >+/*#define CFG_DAVINCI_SDCFG 0x00178622*/ /* 4 banks */ if no need please remove it >+#define CFG_DAVINCI_SDTIM0 0x28923211 >+#define CFG_DAVINCI_SDTIM1 0x0016c722 >+#define CFG_DAVINCI_MMARG_BRF0 0x00444400 >+#define CFG_DAVINCI_PLL1_PLLM 0x15 /* DM6446 = 0x15, DM6441 = 0x12, DM6441_LV = 0x0e */ >+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ > #define PHYS_FLASH_1 0x02000000 /* CS2 Base address */ ^ Whitespace please remove > #define CFG_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */ > #define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */ ^ Whitespace please remove > #define CFG_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CFG_FLASH_SECT_SZ) > #define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SZ /* Env sector Size */ >+#ifdef CFG_USE_INTEL_NOR >+#define CFG_FLASH_SECT_SZ 0x20000 /* 128KB sect size INTEL Flash */ >+#define CFG_FLASH_PROTECTION 1 >+#else >+#define CFG_FLASH_SECT_SZ 0x10000 /* 64KB sect size AMD Flash */ >+#endif > #endif > /*==============================*/ > /* U-Boot general configuration */ > /*==============================*/ > #undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ ^ Whitespace please remove > #define CONFIG_MISC_INIT_R >-#undef CONFIG_BOOTDELAY >+#undef CONFIG_BOOTDELAY >diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h >index 96c9a30..b28405e 100644 >--- a/include/configs/davinci_schmoogie.h >+++ b/include/configs/davinci_schmoogie.h >@@ -35,6 +35,24 @@ > #define CFG_TIMERBASE 0x01c21400 /* use timer 0 */ > #define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */ > #define CFG_HZ 1000 >+#define CFG_DAVINCI_PINMUX_0 0x00000c1f >+#define CFG_DAVINCI_WAITCFG 0x00000000 >+#define CFG_DAVINCI_ACFG2 0x0432229c /* CE configs */ >+#define CFG_DAVINCI_ACFG3 0x3ffffffd >+#define CFG_DAVINCI_ACFG4 0x3ffffffd >+#define CFG_DAVINCI_ACFG5 0x3ffffffd >+#define CFG_DAVINCI_NANDCE 2 /* When using NAND, define 2,3 or 4 */ >+#define CFG_DAVINCI_DDRCTL 0x50006405 /* DDR timing config */ >+#define CFG_DAVINCI_SDREF 0x000005c3 >+/*#define CFG_DAVINCI_SDCFG 0x00178632*/ /* 8 banks */ if no need please remove it >+#define CFG_DAVINCI_SDCFG 0x00178622 /* 4 banks */ >+#define CFG_DAVINCI_SDTIM0 0x28923211 >+#define CFG_DAVINCI_SDTIM1 0x0016c722 >diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h >index de8c4fa..5201a48 100644 >--- a/include/configs/davinci_sonata.h >+++ b/include/configs/davinci_sonata.h >@@ -60,6 +60,24 @@ > #define CFG_TIMERBASE 0x01c21400 /* use timer 0 */ > #define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */ > #define CFG_HZ 1000 >+#define CFG_DAVINCI_PINMUX_0 0x00000c1f >+#define CFG_DAVINCI_WAITCFG 0x00000000 >+#define CFG_DAVINCI_ACFG2 0x3ffffffd /* CE configs */ >+#define CFG_DAVINCI_ACFG3 0x3ffffffd >+#define CFG_DAVINCI_ACFG4 0x3ffffffd >+#define CFG_DAVINCI_ACFG5 0x3ffffffd >+#undef CFG_DAVINCI_NANDCE /* When using NAND, define 2,3 or 4 */ >+#define CFG_DAVINCI_DDRCTL 0x50006405 /* DDR timing config */ >+#define CFG_DAVINCI_SDREF 0x000005c3 >+#define CFG_DAVINCI_SDCFG 0x00178632 /* 8 banks */ >+/*#define CFG_DAVINCI_SDCFG 0x00178622*/ /* 4 banks */ if no need please remove it >+#define CFG_DAVINCI_SDTIM0 0x28923211 >+#define CFG_DAVINCI_SDTIM1 0x0016c722 NB : please do not send patch as attechement Best Regards, J.