From: Wolfgang Denk <wd@denx.de>
Date: Thu, 20 Aug 2009 20:05:50 +0200
Subject: [U-Boot] [PATCH] ppc/85xx: Added PCIe support for P1 P2 RDB
In-Reply-To: <1938B866-A0C2-4152-8085-4BCC4E1A78B9@kernel.crashing.org>
References: <1250775054-20418-1-git-send-email-poonam.aggrwal@freescale.com>
	<20090820151459.C01F3833DBD2@gemini.denx.de>
	<1938B866-A0C2-4152-8085-4BCC4E1A78B9@kernel.crashing.org>
Message-ID: <20090820180550.3ADD0833DBD2@gemini.denx.de>
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To: u-boot@lists.denx.de

Dear Kumar Gala,

In message <1938B866-A0C2-4152-8085-4BCC4E1A78B9@kernel.crashing.org> you wrote:
> 
> > PCIE1 ... pci2 ... pcie1 ???
> >
> > This looks broken to me?
> 
> 
> This is actually correct.. This has to do w/stupid FSL documentation  
> and #.  The device tree "orders" PCI buses based on there register  
> offset in CCSRBAR.  So 0x9000 is pci1, 0xa000 is pci2.  However FSL  
> docs and some internal SoC screwness lists the PCIe controller @ 9000  
> as PCIE2 and the one at A000 as PCIE1.
> 
> Probably should add a comment in the code about this.

Yes, please. This looks just too much like a copy & paste error.

Best regards,

Wolfgang Denk

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