From: Jesse Barnes Subject: [PATCH] drm/i915: fix non-Ironlake 965 class crashes Date: Fri, 23 Apr 2010 09:32:23 -0700 Message-ID: <20100423093223.7adb9861@virtuousgeek.org> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: Sender: linux-kernel-owner@vger.kernel.org To: Linus Torvalds , linux-kernel@vger.kernel.org, intel-gfx@lists.freedesktop.org Cc: Toralf =?UTF-8?B?RsO2cnN0ZXI=?= , eric@anholt.net, Zdenek Kabelac List-Id: intel-gfx@lists.freedesktop.org My PIPE_CONTROL fix (just sent via Eric's tree) was buggy; I was testing a whole set of patches together and missed a conversion to the new HAS_PIPE_CONTROL macro, which will cause breakage on non-Ironlake 965 class chips. Fortunately, the fix is trivial and has been tested. Be sure to use the HAS_PIPE_CONTROL macro in i915_get_gem_seqno, or we'll end up reading the wrong graphics memory, likely causing hangs, crashes, or worse. Reported-by: Zdenek Kabelac Reported-by: Toralf F=C3=B6rster Tested-by: Toralf F=C3=B6rster Signed-off-by: Jesse Barnes diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i91= 5_gem.c index 7f52cc1..ef3d91d 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1793,7 +1793,7 @@ i915_get_gem_seqno(struct drm_device *dev) { drm_i915_private_t *dev_priv =3D dev->dev_private; =20 - if (IS_I965G(dev)) + if (HAS_PIPE_CONTROL(dev)) return ((volatile u32 *)(dev_priv->seqno_page))[0]; else return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);