From: Jesse Barnes Subject: Re: [PATCH 3/5] drm/i915: use PIPE_CONTROL to retire commands Date: Mon, 3 May 2010 12:41:23 -0700 Message-ID: <20100503124123.409f9988@jbarnes-x201> References: <1271875166-13084-1-git-send-email-jbarnes@virtuousgeek.org> <1271875166-13084-4-git-send-email-jbarnes@virtuousgeek.org> <87zl0mne5t.fsf@pollan.anholt.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from outbound-mail-01.bluehost.com (cpoproxy1-pub.bluehost.com [69.89.21.11]) by gabe.freedesktop.org (Postfix) with SMTP id 051869E78C for ; Mon, 3 May 2010 12:41:28 -0700 (PDT) In-Reply-To: <87zl0mne5t.fsf@pollan.anholt.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Eric Anholt Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Thu, 29 Apr 2010 14:26:38 -0700 Eric Anholt wrote: > On Wed, 21 Apr 2010 11:39:24 -0700, Jesse Barnes > wrote: > > This allows us to do less cache flushing on 965+ chipsets. > > I don't think this commit is correct. The ring processing will > continue past the PIPE_CONTROL and on to the MI_USER_INTERRUPT before > the pipeline is flushed. > > I suspect that squashing this with later commits may make for a > correct change, though. Sorry I didn't split these very well; squash them if needed or kick them back to me and I'll repost. Thanks, Jesse