From: Samuel Ortiz Subject: Re: [PATCH 1/2] mfd: wm5102: Expose DRE control registers Date: Tue, 18 Jun 2013 00:38:11 +0200 Message-ID: <20130617223811.GS7998@zurbaran> References: <1371055448-31316-1-git-send-email-ckeepax@opensource.wolfsonmicro.com> <20130612170704.GP1403@sirena.org.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga14.intel.com (mga14.intel.com [143.182.124.37]) by alsa0.perex.cz (Postfix) with ESMTP id 604AF261B2E for ; Tue, 18 Jun 2013 00:38:18 +0200 (CEST) Content-Disposition: inline In-Reply-To: <20130612170704.GP1403@sirena.org.uk> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org To: Mark Brown Cc: alsa-devel@alsa-project.org, tiwai@suse.de, patches@opensource.wolfsonmicro.com, lgirdwood@gmail.com, Charles Keepax List-Id: alsa-devel@alsa-project.org Hi Mark, On Wed, Jun 12, 2013 at 06:07:04PM +0100, Mark Brown wrote: > On Wed, Jun 12, 2013 at 05:44:07PM +0100, Charles Keepax wrote: > > Certain use cases may require specific DRE settings so expose the > > necessary registers. > > Applied both, thanks. Do you have ASoC dependencies on this one or do you mind me taking it ? Cheers, Samuel. -- Intel Open Source Technology Centre http://oss.intel.com/