From: Tom Rini Date: Tue, 20 Aug 2013 15:38:00 -0400 Subject: [U-Boot] [PATCH] ARM: DRA: EMIF: Change DDR3 settings to use hw leveling In-Reply-To: <1377004656-17435-1-git-send-email-r.sricharan@ti.com> References: <1377004656-17435-1-git-send-email-r.sricharan@ti.com> Message-ID: <20130820193800.GD2644@bill-the-cat> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Tue, Aug 20, 2013 at 06:47:36PM +0530, Sricharan R wrote: > Currently the DDR3 memory on DRA7 ES1.0 evm board is enabled using > software leveling. This was done since hardware leveling was not > working. Now that the right sequence to do hw leveling is identified, > use it. This is required for EMIF clockdomain to idle and come back > during lowpower usecases. [snip] > #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS OK, so this reminds me, should we be printing out something more now then, when we're calculating timings, rather than using precalculated ones? Or is that a different issue I'm thinking of? -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 836 bytes Desc: Digital signature URL: