From: Tom Rini Date: Wed, 11 Mar 2015 11:48:20 -0400 Subject: [U-Boot] [PATCH V6 01/11] ARM: Introduce erratum workaround for 798870 In-Reply-To: <1425939129-308-2-git-send-email-nm@ti.com> References: <1425939129-308-1-git-send-email-nm@ti.com> <1425939129-308-2-git-send-email-nm@ti.com> Message-ID: <20150311154820.GF32541@bill-the-cat> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Mon, Mar 09, 2015 at 05:11:59PM -0500, Nishanth Menon wrote: > Add workaround for Cortex-A15 ARM erratum 798870 which says > "If back-to-back speculative cache line fills (fill A and fill B) are > issued from the L1 data cache of a CPU to the L2 cache, the second > request (fill B) is then cancelled, and the second request would have > detected a hazard against a recent write or eviction (write B) to the > same cache line as fill B then the L2 logic might deadlock." > > Implementations for SoC families such as Exynos, OMAP5/DRA7 etc > will be widely different. > > Every SoC has slightly different manner of setting up access to L2ACLR > and similar registers since the Secure Monitor handling of Secure > Monitor Call(smc) is diverse. Hence an weak function is introduced > which may be overriden to implement SoC specific accessor implementation. > > Based on ARM errata Document revision 18.0 (22 Nov 2013) > > Signed-off-by: Nishanth Menon Reviewed-by: Tom Rini -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 836 bytes Desc: Digital signature URL: