Received: from eggs.gnu.org ([2001:4830:134:3::10]:39472) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YyCpL-0005Sr-6f for qemu-devel@nongnu.org; Fri, 29 May 2015 01:27:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YyCpH-00057q-5P for qemu-devel@nongnu.org; Fri, 29 May 2015 01:27:27 -0400 Received: from mail-pa0-x236.google.com ([2607:f8b0:400e:c03::236]:32888) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YyCpG-00057l-Ut for qemu-devel@nongnu.org; Fri, 29 May 2015 01:27:23 -0400 Received: by padbw4 with SMTP id bw4so43062134pad.0 for ; Thu, 28 May 2015 22:27:22 -0700 (PDT) Date: Fri, 29 May 2015 15:22:53 +1000 From: "Edgar E. Iglesias" Message-ID: <20150529052253.GI17116@toto> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Subject: Re: [Qemu-devel] [PATCH v3 7/7] disas: cris: QOMify target specific disas setup List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Crosthwaite Cc: peter.maydell@linaro.org, Peter Crosthwaite , claudio.fontana@huawei.com, qemu-devel@nongnu.org, rth@twiddle.net, afaerber@suse.de, egdar.iglesias@gmail.com On Sun, May 24, 2015 at 03:47:20PM -0700, Peter Crosthwaite wrote: > Move the target_disas() cris specifics to the QOM disas_set_info hook > and delete the cris specific code in disas.c. > > This also now adds support for monitor disas to cris. > > E.g. > (qemu) xp 0x40004000 > 0000000040004000: 0x1e6f25f0 > > And before this patch: > (qemu) xp/i 0x40004000 > 0x40004000: Asm output not supported on this arch > > After: > (qemu) xp/i 0x40004000 > 0x40004000: di > (qemu) xp/i 0x40004002 > 0x40004002: move.d 0xb003c004,$r1 > > Note: second example is 6-byte misaligned instruction! > > Signed-off-by: Peter Crosthwaite Thanks Peter Reviewed-by: Edgar E. Iglesias > --- > disas.c | 8 -------- > target-cris/cpu.c | 16 ++++++++++++++++ > 2 files changed, 16 insertions(+), 8 deletions(-) > > diff --git a/disas.c b/disas.c > index 937e08b..69a6066 100644 > --- a/disas.c > +++ b/disas.c > @@ -257,14 +257,6 @@ void target_disas(FILE *out, CPUState *cpu, target_ulong code, > #elif defined(TARGET_ALPHA) > s.info.mach = bfd_mach_alpha_ev6; > s.info.print_insn = print_insn_alpha; > -#elif defined(TARGET_CRIS) > - if (flags != 32) { > - s.info.mach = bfd_mach_cris_v0_v10; > - s.info.print_insn = print_insn_crisv10; > - } else { > - s.info.mach = bfd_mach_cris_v32; > - s.info.print_insn = print_insn_crisv32; > - } > #elif defined(TARGET_S390X) > s.info.mach = bfd_mach_s390_64; > s.info.print_insn = print_insn_s390; > diff --git a/target-cris/cpu.c b/target-cris/cpu.c > index 16cfba9..d555ea0 100644 > --- a/target-cris/cpu.c > +++ b/target-cris/cpu.c > @@ -161,6 +161,20 @@ static void cris_cpu_set_irq(void *opaque, int irq, int level) > } > #endif > > +static void cris_disas_set_info(CPUState *cpu, disassemble_info *info) > +{ > + CRISCPU *cc = CRIS_CPU(cpu); > + CPUCRISState *env = &cc->env; > + > + if (env->pregs[PR_VR] != 32) { > + info->mach = bfd_mach_cris_v0_v10; > + info->print_insn = print_insn_crisv10; > + } else { > + info->mach = bfd_mach_cris_v32; > + info->print_insn = print_insn_crisv32; > + } > +} > + > static void cris_cpu_initfn(Object *obj) > { > CPUState *cs = CPU(obj); > @@ -292,6 +306,8 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data) > > cc->gdb_num_core_regs = 49; > cc->gdb_stop_before_watchpoint = true; > + > + cc->disas_set_info = cris_disas_set_info; > } > > static const TypeInfo cris_cpu_type_info = { > -- > 1.9.1 > >