Date: Tue, 2 Jun 2015 13:05:09 +0200
From: Aurelien Jarno <aurelien@aurel32.net>
Message-ID: <20150602110508.GO26298@aurel32.net>
References: <1432729200-5322-1-git-send-email-hpoussin@reactos.org>
	<1432729200-5322-16-git-send-email-hpoussin@reactos.org>
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In-Reply-To: <1432729200-5322-16-git-send-email-hpoussin@reactos.org>
Sender: Aurelien Jarno <aurelien@aurel32.net>
Subject: Re: [Qemu-devel] [PATCH v2 15/17] net/dp8393x: fix hardware reset
To: =?iso-8859-15?Q?Herv=E9?= Poussineau <hpoussin@reactos.org>
Cc: Leon Alrae <leon.alrae@imgtec.com>, qemu-devel@nongnu.org

On 2015-05-27 14:19, Herv=E9 Poussineau wrote:
> Documentation is not clear of what happens when doing a hardware reset,
> but firmware expect all registers to be zero unless specified otherwise.
>=20
> This fixes reboot on MIPS Magnum.
>=20
> Signed-off-by: Herv=E9 Poussineau <hpoussin@reactos.org>
> ---
>  hw/net/dp8393x.c | 1 +
>  1 file changed, 1 insertion(+)
>=20
> diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c
> index b72b0b1..95a4d3d 100644
> --- a/hw/net/dp8393x.c
> +++ b/hw/net/dp8393x.c
> @@ -786,6 +786,7 @@ static void dp8393x_reset(DeviceState *dev)
>      dp8393xState *s =3D DP8393X(dev);
>      timer_del(s->watchdog);
> =20
> +    memset(s->regs, 0, sizeof(s->regs));
>      s->regs[SONIC_CR] =3D SONIC_CR_RST | SONIC_CR_STP | SONIC_CR_RXDIS;
>      s->regs[SONIC_DCR] &=3D ~(SONIC_DCR_EXBUS | SONIC_DCR_LBR);
>      s->regs[SONIC_RCR] &=3D ~(SONIC_RCR_LB0 | SONIC_RCR_LB1 | SONIC_RCR_=
BRD | SONIC_RCR_RNT);

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>

--=20
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
aurelien@aurel32.net                 http://www.aurel32.net