From: Marek Vasut <marex@denx.de>
Date: Sat, 17 Oct 2015 02:15:12 +0200
Subject: [U-Boot] [PATCHv2] arm: socfpga: enable data/inst prefetch and
	shared override in the L2
In-Reply-To: <1444922016-3501-1-git-send-email-dinguyen@opensource.altera.com>
References: <1444922016-3501-1-git-send-email-dinguyen@opensource.altera.com>
Message-ID: <201510170215.12369.marex@denx.de>
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To: u-boot@lists.denx.de

On Thursday, October 15, 2015 at 05:13:36 PM, dinguyen at opensource.altera.com 
wrote:
> From: Dinh Nguyen <dinguyen@opensource.altera.com>
> 
> Update the L2 AUX CTRL settings for the SoCFPGA.
> 
> Enabling D and I prefetch bits helps improve SDRAM performance on the
> platform.
> 
> Also, we need to enable bit 22 of the L2. By not having bit 22 set in the
> PL310 Auxiliary Control register (shared attribute override enable) has the
> side effect of transforming Normal Shared Non-cacheable reads into
> Cacheable no-allocate reads.
> 
> Coherent DMA buffers in Linux always have a Cacheable alias via the
> kernel linear mapping and the processor can speculatively load cache
> lines into the PL310 controller. With bit 22 cleared, Non-cacheable
> reads would unexpectedly hit such cache lines leading to buffer
> corruption.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>

Applied, thanks!

Best regards,
Marek Vasut