From: Tom Rini Date: Wed, 18 Nov 2015 17:36:50 -0500 Subject: [U-Boot] [U-Boot, v2, 08/15] powerpc/km8321: define CONFIG_SYS_DDRCDR In-Reply-To: <1447754018-12365-9-git-send-email-valentin.longchamp@keymile.com> References: <1447754018-12365-9-git-send-email-valentin.longchamp@keymile.com> Message-ID: <20151118223650.GP8060@bill-the-cat> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Tue, Nov 17, 2015 at 10:53:31AM +0100, Valentin Longchamp wrote: > On the km8321 boards is CONFIG_SYS_DDRCDR not defined, which leads to > the DDRCDR not being configured at startup and still containing the > reset value. > > The required settings for our km8321 hardware designs are different than > the reset value and must be set with CONFIG_SYS_DDRCDR, that is used > by mpc83xx's cpu_init_f function at early CPU initialization. > > The important settings are the DDR2 internal voltage level and the > half-strength "drivers". > > In our case where the DRAM chips are soldered on board and the routing > for these signals under control, half-strength is sufficient as a few > measurements done in the lasts have shown. Since all the hardware > qualification tests have been performed with half strength, the nominal > strength settings are removed in favor of the default reset half > strength settings. > > Signed-off-by: Valentin Longchamp Applied to u-boot/master, thanks! -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 836 bytes Desc: Digital signature URL: