From: Bruce Richardson Subject: [PATCH 3/3] build/x86: add SSE cpuflags Date: Wed, 20 Sep 2017 11:51:07 +0100 Message-ID: <20170920105107.153935-4-bruce.richardson@intel.com> References: <20170920105107.153935-1-bruce.richardson@intel.com> Cc: Bruce Richardson To: dev@dpdk.org Return-path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 422ED1B1A0 for ; Wed, 20 Sep 2017 12:58:19 +0200 (CEST) In-Reply-To: <20170920105107.153935-1-bruce.richardson@intel.com> List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Previous code only added in AVX, and a few other non-SSE flags to the compile-time cpuflags because all SSE instruction set levels are now required for an x86 build. However, some apps may still be checking for the existing SSE ones in the legacy build system, so add them here for completeness and compatibility. Signed-off-by: Bruce Richardson --- config/x86/meson.build | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/config/x86/meson.build b/config/x86/meson.build index 0d1a532ad..c05c2f418 100644 --- a/config/x86/meson.build +++ b/config/x86/meson.build @@ -40,6 +40,12 @@ if cc.get_define('__SSE4_2__', args: march_opt) == '' error(sse_errormsg) endif +base_flags = ['SSE', 'SSE2', 'SSE3','SSSE3', 'SSE4_1', 'SSE4_2'] +foreach f:base_flags + dpdk_conf.set('RTE_MACHINE_CPUFLAG_' + f, 1) + compile_time_cpuflags += ['RTE_CPUFLAG_' + f] +endforeach + dpdk_conf.set('RTE_ARCH_X86', 1) if (host_machine.cpu_family() == 'x86_64') dpdk_conf.set('RTE_ARCH_X86_64', 1) @@ -66,5 +72,9 @@ if cc.get_define('__AVX2__', args: march_opt) != '' dpdk_conf.set('RTE_MACHINE_CPUFLAG_AVX2', 1) compile_time_cpuflags += ['RTE_CPUFLAG_AVX2'] endif +if cc.get_define('__AVX512F__', args: march_opt) != '' + dpdk_conf.set('RTE_MACHINE_CPUFLAG_AVX512F', 1) + compile_time_cpuflags += ['RTE_CPUFLAG_AVX512F'] +endif dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64) -- 2.13.5