Received: from eggs.gnu.org ([2001:4830:134:3::10]:39929) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1emWZ7-0004OT-Ex for qemu-devel@nongnu.org; Thu, 15 Feb 2018 22:20:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1emWZ3-0003EO-Dt for qemu-devel@nongnu.org; Thu, 15 Feb 2018 22:20:01 -0500 Date: Fri, 16 Feb 2018 14:06:30 +1100 From: David Gibson Message-ID: <20180216030630.GC2074@umbus.fritz.box> References: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="eRtJSFbw+EEWtPj3" Content-Disposition: inline In-Reply-To: Subject: Re: [Qemu-devel] [PATCH v2 1/3] ppc4xx: Add device models found in PPC440 core SoCs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: BALATON Zoltan Cc: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, Alexander Graf , Francois Revol --eRtJSFbw+EEWtPj3 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Feb 15, 2018 at 10:27:06PM +0100, BALATON Zoltan wrote: > These devices are found in newer SoCs based on 440 core e.g. the 460EX > (http://www.embeddeddeveloper.com/assets/processors/amcc/datasheets/ > PP460EX_DS2063.pdf) >=20 > Signed-off-by: BALATON Zoltan Applied, thanks. > --- >=20 > v2: > - Rebased to latest changes on master > - Removed printfs >=20 > hw/ppc/ppc440.h | 26 + > hw/ppc/ppc440_uc.c | 1159 ++++++++++++++++++++++++++++++++++++++= ++++++ > include/hw/pci/pcie_host.h | 2 +- > 3 files changed, 1186 insertions(+), 1 deletion(-) > create mode 100644 hw/ppc/ppc440.h > create mode 100644 hw/ppc/ppc440_uc.c >=20 > diff --git a/hw/ppc/ppc440.h b/hw/ppc/ppc440.h > new file mode 100644 > index 0000000..ad27db1 > --- /dev/null > +++ b/hw/ppc/ppc440.h > @@ -0,0 +1,26 @@ > +/* > + * QEMU PowerPC 440 shared definitions > + * > + * Copyright (c) 2012 Fran=E7ois Revol > + * Copyright (c) 2016-2018 BALATON Zoltan > + * > + * This work is licensed under the GNU GPL license version 2 or later. > + * > + */ > + > +#ifndef PPC440_H > +#define PPC440_H > + > +#include "hw/ppc/ppc.h" > + > +void ppc4xx_l2sram_init(CPUPPCState *env); > +void ppc4xx_cpr_init(CPUPPCState *env); > +void ppc4xx_sdr_init(CPUPPCState *env); > +void ppc440_sdram_init(CPUPPCState *env, int nbanks, > + MemoryRegion *ram_memories, > + hwaddr *ram_bases, hwaddr *ram_sizes, > + int do_init); > +void ppc4xx_ahb_init(CPUPPCState *env); > +void ppc460ex_pcie_init(CPUPPCState *env); > + > +#endif /* PPC440_H */ > diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c > new file mode 100644 > index 0000000..4e2523a > --- /dev/null > +++ b/hw/ppc/ppc440_uc.c > @@ -0,0 +1,1159 @@ > +/* > + * QEMU PowerPC 440 embedded processors emulation > + * > + * Copyright (c) 2012 Fran=E7ois Revol > + * Copyright (c) 2016-2018 BALATON Zoltan > + * > + * This work is licensed under the GNU GPL license version 2 or later. > + * > + */ > + > +#include "qemu/osdep.h" > +#include "qemu-common.h" > +#include "qemu/cutils.h" > +#include "qemu/error-report.h" > +#include "qapi/error.h" > +#include "cpu.h" > +#include "hw/hw.h" > +#include "exec/address-spaces.h" > +#include "exec/memory.h" > +#include "hw/ppc/ppc.h" > +#include "hw/pci/pci.h" > +#include "sysemu/block-backend.h" > +#include "hw/ppc/ppc440.h" > + > +/***********************************************************************= ******/ > +/* L2 Cache as SRAM */ > +/* FIXME:fix names */ > +enum { > + DCR_L2CACHE_BASE =3D 0x30, > + DCR_L2CACHE_CFG =3D DCR_L2CACHE_BASE, > + DCR_L2CACHE_CMD, > + DCR_L2CACHE_ADDR, > + DCR_L2CACHE_DATA, > + DCR_L2CACHE_STAT, > + DCR_L2CACHE_CVER, > + DCR_L2CACHE_SNP0, > + DCR_L2CACHE_SNP1, > + DCR_L2CACHE_END =3D DCR_L2CACHE_SNP1, > +}; > + > +/* base is 460ex-specific, cf. U-Boot, ppc4xx-isram.h */ > +enum { > + DCR_ISRAM0_BASE =3D 0x20, > + DCR_ISRAM0_SB0CR =3D DCR_ISRAM0_BASE, > + DCR_ISRAM0_SB1CR, > + DCR_ISRAM0_SB2CR, > + DCR_ISRAM0_SB3CR, > + DCR_ISRAM0_BEAR, > + DCR_ISRAM0_BESR0, > + DCR_ISRAM0_BESR1, > + DCR_ISRAM0_PMEG, > + DCR_ISRAM0_CID, > + DCR_ISRAM0_REVID, > + DCR_ISRAM0_DPC, > + DCR_ISRAM0_END =3D DCR_ISRAM0_DPC > +}; > + > +enum { > + DCR_ISRAM1_BASE =3D 0xb0, > + DCR_ISRAM1_SB0CR =3D DCR_ISRAM1_BASE, > + /* single bank */ > + DCR_ISRAM1_BEAR =3D DCR_ISRAM1_BASE + 0x04, > + DCR_ISRAM1_BESR0, > + DCR_ISRAM1_BESR1, > + DCR_ISRAM1_PMEG, > + DCR_ISRAM1_CID, > + DCR_ISRAM1_REVID, > + DCR_ISRAM1_DPC, > + DCR_ISRAM1_END =3D DCR_ISRAM1_DPC > +}; > + > +typedef struct ppc4xx_l2sram_t { > + MemoryRegion bank[4]; > + uint32_t l2cache[8]; > + uint32_t isram0[11]; > +} ppc4xx_l2sram_t; > + > +#ifdef MAP_L2SRAM > +static void l2sram_update_mappings(ppc4xx_l2sram_t *l2sram, > + uint32_t isarc, uint32_t isacntl, > + uint32_t dsarc, uint32_t dsacntl) > +{ > + if (l2sram->isarc !=3D isarc || > + (l2sram->isacntl & 0x80000000) !=3D (isacntl & 0x80000000)) { > + if (l2sram->isacntl & 0x80000000) { > + /* Unmap previously assigned memory region */ > + memory_region_del_subregion(get_system_memory(), > + &l2sram->isarc_ram); > + } > + if (isacntl & 0x80000000) { > + /* Map new instruction memory region */ > + memory_region_add_subregion(get_system_memory(), isarc, > + &l2sram->isarc_ram); > + } > + } > + if (l2sram->dsarc !=3D dsarc || > + (l2sram->dsacntl & 0x80000000) !=3D (dsacntl & 0x80000000)) { > + if (l2sram->dsacntl & 0x80000000) { > + /* Beware not to unmap the region we just mapped */ > + if (!(isacntl & 0x80000000) || l2sram->dsarc !=3D isarc) { > + /* Unmap previously assigned memory region */ > + memory_region_del_subregion(get_system_memory(), > + &l2sram->dsarc_ram); > + } > + } > + if (dsacntl & 0x80000000) { > + /* Beware not to remap the region we just mapped */ > + if (!(isacntl & 0x80000000) || dsarc !=3D isarc) { > + /* Map new data memory region */ > + memory_region_add_subregion(get_system_memory(), dsarc, > + &l2sram->dsarc_ram); > + } > + } > + } > +} > +#endif > + > +static uint32_t dcr_read_l2sram(void *opaque, int dcrn) > +{ > + ppc4xx_l2sram_t *l2sram =3D opaque; > + uint32_t ret =3D 0; > + > + switch (dcrn) { > + case DCR_L2CACHE_CFG: > + case DCR_L2CACHE_CMD: > + case DCR_L2CACHE_ADDR: > + case DCR_L2CACHE_DATA: > + case DCR_L2CACHE_STAT: > + case DCR_L2CACHE_CVER: > + case DCR_L2CACHE_SNP0: > + case DCR_L2CACHE_SNP1: > + ret =3D l2sram->l2cache[dcrn - DCR_L2CACHE_BASE]; > + break; > + > + case DCR_ISRAM0_SB0CR: > + case DCR_ISRAM0_SB1CR: > + case DCR_ISRAM0_SB2CR: > + case DCR_ISRAM0_SB3CR: > + case DCR_ISRAM0_BEAR: > + case DCR_ISRAM0_BESR0: > + case DCR_ISRAM0_BESR1: > + case DCR_ISRAM0_PMEG: > + case DCR_ISRAM0_CID: > + case DCR_ISRAM0_REVID: > + case DCR_ISRAM0_DPC: > + ret =3D l2sram->isram0[dcrn - DCR_ISRAM0_BASE]; > + break; > + > + default: > + break; > + } > + > + return ret; > +} > + > +static void dcr_write_l2sram(void *opaque, int dcrn, uint32_t val) > +{ > + /*ppc4xx_l2sram_t *l2sram =3D opaque;*/ > + /* FIXME: Actually handle L2 cache mapping */ > + > + switch (dcrn) { > + case DCR_L2CACHE_CFG: > + case DCR_L2CACHE_CMD: > + case DCR_L2CACHE_ADDR: > + case DCR_L2CACHE_DATA: > + case DCR_L2CACHE_STAT: > + case DCR_L2CACHE_CVER: > + case DCR_L2CACHE_SNP0: > + case DCR_L2CACHE_SNP1: > + /*l2sram->l2cache[dcrn - DCR_L2CACHE_BASE] =3D val;*/ > + break; > + > + case DCR_ISRAM0_SB0CR: > + case DCR_ISRAM0_SB1CR: > + case DCR_ISRAM0_SB2CR: > + case DCR_ISRAM0_SB3CR: > + case DCR_ISRAM0_BEAR: > + case DCR_ISRAM0_BESR0: > + case DCR_ISRAM0_BESR1: > + case DCR_ISRAM0_PMEG: > + case DCR_ISRAM0_CID: > + case DCR_ISRAM0_REVID: > + case DCR_ISRAM0_DPC: > + /*l2sram->isram0[dcrn - DCR_L2CACHE_BASE] =3D val;*/ > + break; > + > + case DCR_ISRAM1_SB0CR: > + case DCR_ISRAM1_BEAR: > + case DCR_ISRAM1_BESR0: > + case DCR_ISRAM1_BESR1: > + case DCR_ISRAM1_PMEG: > + case DCR_ISRAM1_CID: > + case DCR_ISRAM1_REVID: > + case DCR_ISRAM1_DPC: > + /*l2sram->isram1[dcrn - DCR_L2CACHE_BASE] =3D val;*/ > + break; > + } > + /*l2sram_update_mappings(l2sram, isarc, isacntl, dsarc, dsacntl);*/ > +} > + > +static void l2sram_reset(void *opaque) > +{ > + ppc4xx_l2sram_t *l2sram =3D opaque; > + > + memset(l2sram->l2cache, 0, sizeof(l2sram->l2cache)); > + l2sram->l2cache[DCR_L2CACHE_STAT - DCR_L2CACHE_BASE] =3D 0x80000000; > + memset(l2sram->isram0, 0, sizeof(l2sram->isram0)); > + /*l2sram_update_mappings(l2sram, isarc, isacntl, dsarc, dsacntl);*/ > +} > + > +void ppc4xx_l2sram_init(CPUPPCState *env) > +{ > + ppc4xx_l2sram_t *l2sram; > + > + l2sram =3D g_malloc0(sizeof(*l2sram)); > + /* XXX: Size is 4*64kB for 460ex, cf. U-Boot, ppc4xx-isram.h */ > + memory_region_init_ram(&l2sram->bank[0], NULL, "ppc4xx.l2sram_bank0", > + 64 * K_BYTE, &error_abort); > + memory_region_init_ram(&l2sram->bank[1], NULL, "ppc4xx.l2sram_bank1", > + 64 * K_BYTE, &error_abort); > + memory_region_init_ram(&l2sram->bank[2], NULL, "ppc4xx.l2sram_bank2", > + 64 * K_BYTE, &error_abort); > + memory_region_init_ram(&l2sram->bank[3], NULL, "ppc4xx.l2sram_bank3", > + 64 * K_BYTE, &error_abort); > + qemu_register_reset(&l2sram_reset, l2sram); > + ppc_dcr_register(env, DCR_L2CACHE_CFG, > + l2sram, &dcr_read_l2sram, &dcr_write_l2sram); > + ppc_dcr_register(env, DCR_L2CACHE_CMD, > + l2sram, &dcr_read_l2sram, &dcr_write_l2sram); > + ppc_dcr_register(env, DCR_L2CACHE_ADDR, > + l2sram, &dcr_read_l2sram, &dcr_write_l2sram); > + ppc_dcr_register(env, DCR_L2CACHE_DATA, > + l2sram, &dcr_read_l2sram, &dcr_write_l2sram); > + ppc_dcr_register(env, DCR_L2CACHE_STAT, > + l2sram, &dcr_read_l2sram, &dcr_write_l2sram); > + ppc_dcr_register(env, DCR_L2CACHE_CVER, > + l2sram, &dcr_read_l2sram, &dcr_write_l2sram); > + ppc_dcr_register(env, DCR_L2CACHE_SNP0, > + l2sram, &dcr_read_l2sram, &dcr_write_l2sram); > + ppc_dcr_register(env, DCR_L2CACHE_SNP1, > + l2sram, &dcr_read_l2sram, &dcr_write_l2sram); > + > + ppc_dcr_register(env, DCR_ISRAM0_SB0CR, > + l2sram, &dcr_read_l2sram, &dcr_write_l2sram); > + ppc_dcr_register(env, DCR_ISRAM0_SB1CR, > + l2sram, &dcr_read_l2sram, &dcr_write_l2sram); > + ppc_dcr_register(env, DCR_ISRAM0_SB2CR, > + l2sram, &dcr_read_l2sram, &dcr_write_l2sram); > + ppc_dcr_register(env, DCR_ISRAM0_SB3CR, > + l2sram, &dcr_read_l2sram, &dcr_write_l2sram); > + ppc_dcr_register(env, DCR_ISRAM0_PMEG, > + l2sram, &dcr_read_l2sram, &dcr_write_l2sram); > + ppc_dcr_register(env, DCR_ISRAM0_DPC, > + l2sram, &dcr_read_l2sram, &dcr_write_l2sram); > + > + ppc_dcr_register(env, DCR_ISRAM1_SB0CR, > + l2sram, &dcr_read_l2sram, &dcr_write_l2sram); > + ppc_dcr_register(env, DCR_ISRAM1_PMEG, > + l2sram, &dcr_read_l2sram, &dcr_write_l2sram); > + ppc_dcr_register(env, DCR_ISRAM1_DPC, > + l2sram, &dcr_read_l2sram, &dcr_write_l2sram); > +} > + > +/***********************************************************************= ******/ > +/* Clocking Power on Reset */ > +enum { > + CPR0_CFGADDR =3D 0xC, > + CPR0_CFGDATA =3D 0xD, > + > + CPR0_PLLD =3D 0x060, > + CPR0_PLBED =3D 0x080, > + CPR0_OPBD =3D 0x0C0, > + CPR0_PERD =3D 0x0E0, > + CPR0_AHBD =3D 0x100, > +}; > + > +typedef struct ppc4xx_cpr_t { > + uint32_t addr; > +} ppc4xx_cpr_t; > + > +static uint32_t dcr_read_cpr(void *opaque, int dcrn) > +{ > + ppc4xx_cpr_t *cpr =3D opaque; > + uint32_t ret =3D 0; > + > + switch (dcrn) { > + case CPR0_CFGADDR: > + ret =3D cpr->addr; > + break; > + case CPR0_CFGDATA: > + switch (cpr->addr) { > + case CPR0_PLLD: > + ret =3D (0xb5 << 24) | (1 << 16) | (9 << 8); > + break; > + case CPR0_PLBED: > + ret =3D (5 << 24); > + break; > + case CPR0_OPBD: > + ret =3D (2 << 24); > + break; > + case CPR0_PERD: > + case CPR0_AHBD: > + ret =3D (1 << 24); > + break; > + default: > + break; > + } > + break; > + default: > + break; > + } > + > + return ret; > +} > + > +static void dcr_write_cpr(void *opaque, int dcrn, uint32_t val) > +{ > + ppc4xx_cpr_t *cpr =3D opaque; > + > + switch (dcrn) { > + case CPR0_CFGADDR: > + cpr->addr =3D val; > + break; > + case CPR0_CFGDATA: > + break; > + default: > + break; > + } > +} > + > +static void ppc4xx_cpr_reset(void *opaque) > +{ > + ppc4xx_cpr_t *cpr =3D opaque; > + > + cpr->addr =3D 0; > +} > + > +void ppc4xx_cpr_init(CPUPPCState *env) > +{ > + ppc4xx_cpr_t *cpr; > + > + cpr =3D g_malloc0(sizeof(*cpr)); > + ppc_dcr_register(env, CPR0_CFGADDR, cpr, &dcr_read_cpr, &dcr_write_c= pr); > + ppc_dcr_register(env, CPR0_CFGDATA, cpr, &dcr_read_cpr, &dcr_write_c= pr); > + qemu_register_reset(ppc4xx_cpr_reset, cpr); > +} > + > +/***********************************************************************= ******/ > +/* System DCRs */ > +typedef struct ppc4xx_sdr_t ppc4xx_sdr_t; > +struct ppc4xx_sdr_t { > + uint32_t addr; > +}; > + > +enum { > + SDR0_CFGADDR =3D 0x00e, > + SDR0_CFGDATA, > + SDR0_STRP0 =3D 0x020, > + SDR0_STRP1, > + SDR0_102 =3D 0x66, > + SDR0_103, > + SDR0_128 =3D 0x80, > + SDR0_ECID3 =3D 0x083, > + SDR0_DDR0 =3D 0x0e1, > + SDR0_USB0 =3D 0x320, > +}; > + > +enum { > + PESDR0_LOOP =3D 0x303, > + PESDR0_RCSSET, > + PESDR0_RCSSTS, > + PESDR0_RSTSTA =3D 0x310, > + PESDR1_LOOP =3D 0x343, > + PESDR1_RCSSET, > + PESDR1_RCSSTS, > + PESDR1_RSTSTA =3D 0x365, > +}; > + > +#define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n)) & 0x03) << 29) > +#define SDR0_DDR0_DDRM_DDR1 0x20000000 > +#define SDR0_DDR0_DDRM_DDR2 0x40000000 > + > +static uint32_t dcr_read_sdr(void *opaque, int dcrn) > +{ > + ppc4xx_sdr_t *sdr =3D opaque; > + uint32_t ret =3D 0; > + > + switch (dcrn) { > + case SDR0_CFGADDR: > + ret =3D sdr->addr; > + break; > + case SDR0_CFGDATA: > + switch (sdr->addr) { > + case SDR0_STRP0: > + /* FIXME: Is this correct? This breaks timing in U-Boot */ > + ret =3D 0; /*(0xb5 << 8) | (1 << 4) | 9 */ > + break; > + case SDR0_STRP1: > + ret =3D (5 << 29) | (2 << 26) | (1 << 24); > + break; > + case SDR0_ECID3: > + ret =3D 1 << 20; /* No Security/Kasumi support */ > + break; > + case SDR0_DDR0: > + ret =3D SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1; > + break; > + case PESDR0_RCSSET: > + case PESDR1_RCSSET: > + ret =3D (1 << 24) | (1 << 16); > + break; > + case PESDR0_RCSSTS: > + case PESDR1_RCSSTS: > + ret =3D (1 << 16) | (1 << 12); > + break; > + case PESDR0_RSTSTA: > + case PESDR1_RSTSTA: > + ret =3D 1; > + break; > + case PESDR0_LOOP: > + case PESDR1_LOOP: > + ret =3D 1 << 12; > + break; > + default: > + break; > + } > + break; > + default: > + break; > + } > + > + return ret; > +} > + > +static void dcr_write_sdr(void *opaque, int dcrn, uint32_t val) > +{ > + ppc4xx_sdr_t *sdr =3D opaque; > + > + switch (dcrn) { > + case SDR0_CFGADDR: > + sdr->addr =3D val; > + break; > + case SDR0_CFGDATA: > + switch (sdr->addr) { > + case 0x00: /* B0CR */ > + break; > + default: > + break; > + } > + break; > + default: > + break; > + } > +} > + > +static void sdr_reset(void *opaque) > +{ > + ppc4xx_sdr_t *sdr =3D opaque; > + > + sdr->addr =3D 0; > +} > + > +void ppc4xx_sdr_init(CPUPPCState *env) > +{ > + ppc4xx_sdr_t *sdr; > + > + sdr =3D g_malloc0(sizeof(*sdr)); > + qemu_register_reset(&sdr_reset, sdr); > + ppc_dcr_register(env, SDR0_CFGADDR, > + sdr, &dcr_read_sdr, &dcr_write_sdr); > + ppc_dcr_register(env, SDR0_CFGDATA, > + sdr, &dcr_read_sdr, &dcr_write_sdr); > + ppc_dcr_register(env, SDR0_102, > + sdr, &dcr_read_sdr, &dcr_write_sdr); > + ppc_dcr_register(env, SDR0_103, > + sdr, &dcr_read_sdr, &dcr_write_sdr); > + ppc_dcr_register(env, SDR0_128, > + sdr, &dcr_read_sdr, &dcr_write_sdr); > + ppc_dcr_register(env, SDR0_USB0, > + sdr, &dcr_read_sdr, &dcr_write_sdr); > +} > + > +/***********************************************************************= ******/ > +/* SDRAM controller */ > +typedef struct ppc4xx_sdram_t { > + uint32_t addr; > + int nbanks; > + MemoryRegion containers[4]; /* used for clipping */ > + MemoryRegion *ram_memories; > + hwaddr ram_bases[4]; > + hwaddr ram_sizes[4]; > + uint32_t bcr[4]; > +} ppc4xx_sdram_t; > + > +enum { > + SDRAM0_CFGADDR =3D 0x10, > + SDRAM0_CFGDATA, > + SDRAM_R0BAS =3D 0x40, > + SDRAM_R1BAS, > + SDRAM_R2BAS, > + SDRAM_R3BAS, > + SDRAM_CONF1HB =3D 0x45, > + SDRAM_PLBADDULL =3D 0x4a, > + SDRAM_CONF1LL =3D 0x4b, > + SDRAM_CONFPATHB =3D 0x4f, > + SDRAM_PLBADDUHB =3D 0x50, > +}; > + > +/* XXX: TOFIX: some patches have made this code become inconsistent: > + * there are type inconsistencies, mixing hwaddr, target_ulong > + * and uint32_t > + */ > +static uint32_t sdram_bcr(hwaddr ram_base, hwaddr ram_size) > +{ > + uint32_t bcr; > + > + switch (ram_size) { > + case (8 * M_BYTE): > + bcr =3D 0xffc0; > + break; > + case (16 * M_BYTE): > + bcr =3D 0xff80; > + break; > + case (32 * M_BYTE): > + bcr =3D 0xff00; > + break; > + case (64 * M_BYTE): > + bcr =3D 0xfe00; > + break; > + case (128 * M_BYTE): > + bcr =3D 0xfc00; > + break; > + case (256 * M_BYTE): > + bcr =3D 0xf800; > + break; > + case (512 * M_BYTE): > + bcr =3D 0xf000; > + break; > + case (1 * G_BYTE): > + bcr =3D 0xe000; > + break; > + default: > + error_report("invalid RAM size " TARGET_FMT_plx, ram_size); > + return 0; > + } > + bcr |=3D ram_base & 0xFF800000; > + bcr |=3D 1; > + > + return bcr; > +} > + > +static inline hwaddr sdram_base(uint32_t bcr) > +{ > + return bcr & 0xFF800000; > +} > + > +static target_ulong sdram_size(uint32_t bcr) > +{ > + target_ulong size; > + int sh; > + > + sh =3D 1024 - ((bcr >> 6) & 0x3ff); > + if (sh =3D=3D 0) { > + size =3D -1; > + } else { > + size =3D 8 * M_BYTE * sh; > + } > + > + return size; > +} > + > +static void sdram_set_bcr(ppc4xx_sdram_t *sdram, > + uint32_t *bcrp, uint32_t bcr, int enabled) > +{ > + unsigned n =3D bcrp - sdram->bcr; > + > + if (*bcrp & 1) { > + /* Unmap RAM */ > + memory_region_del_subregion(get_system_memory(), > + &sdram->containers[n]); > + memory_region_del_subregion(&sdram->containers[n], > + &sdram->ram_memories[n]); > + object_unparent(OBJECT(&sdram->containers[n])); > + } > + *bcrp =3D bcr & 0xFFDEE001; > + if (enabled && (bcr & 1)) { > + memory_region_init(&sdram->containers[n], NULL, "sdram-container= s", > + sdram_size(bcr)); > + memory_region_add_subregion(&sdram->containers[n], 0, > + &sdram->ram_memories[n]); > + memory_region_add_subregion(get_system_memory(), > + sdram_base(bcr), > + &sdram->containers[n]); > + } > +} > + > +static void sdram_map_bcr(ppc4xx_sdram_t *sdram) > +{ > + int i; > + > + for (i =3D 0; i < sdram->nbanks; i++) { > + if (sdram->ram_sizes[i] !=3D 0) { > + sdram_set_bcr(sdram, > + &sdram->bcr[i], > + sdram_bcr(sdram->ram_bases[i], sdram->ram_size= s[i]), > + 1); > + } else { > + sdram_set_bcr(sdram, &sdram->bcr[i], 0, 0); > + } > + } > +} > + > +static uint32_t dcr_read_sdram(void *opaque, int dcrn) > +{ > + ppc4xx_sdram_t *sdram =3D opaque; > + uint32_t ret =3D 0; > + > + switch (dcrn) { > + case SDRAM_R0BAS: > + case SDRAM_R1BAS: > + case SDRAM_R2BAS: > + case SDRAM_R3BAS: > + ret =3D sdram_bcr(sdram->ram_bases[dcrn - SDRAM_R0BAS], > + sdram->ram_sizes[dcrn - SDRAM_R0BAS]); > + break; > + case SDRAM_CONF1HB: > + case SDRAM_CONF1LL: > + case SDRAM_CONFPATHB: > + case SDRAM_PLBADDULL: > + case SDRAM_PLBADDUHB: > + break; > + case SDRAM0_CFGADDR: > + ret =3D sdram->addr; > + break; > + case SDRAM0_CFGDATA: > + switch (sdram->addr) { > + case 0x14: /* SDRAM_MCSTAT (405EX) */ > + case 0x1F: > + ret =3D 0x80000000; > + break; > + case 0x21: /* SDRAM_MCOPT2 */ > + ret =3D 0x08000000; > + break; > + case 0x40: /* SDRAM_MB0CF */ > + ret =3D 0x00008001; > + break; > + case 0x7A: /* SDRAM_DLCR */ > + ret =3D 0x02000000; > + break; > + case 0xE1: /* SDR0_DDR0 */ > + ret =3D SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1; > + break; > + default: > + break; > + } > + break; > + default: > + break; > + } > + > + return ret; > +} > + > +static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val) > +{ > + ppc4xx_sdram_t *sdram =3D opaque; > + > + switch (dcrn) { > + case SDRAM_R0BAS: > + case SDRAM_R1BAS: > + case SDRAM_R2BAS: > + case SDRAM_R3BAS: > + case SDRAM_CONF1HB: > + case SDRAM_CONF1LL: > + case SDRAM_CONFPATHB: > + case SDRAM_PLBADDULL: > + case SDRAM_PLBADDUHB: > + break; > + case SDRAM0_CFGADDR: > + sdram->addr =3D val; > + break; > + case SDRAM0_CFGDATA: > + switch (sdram->addr) { > + case 0x00: /* B0CR */ > + break; > + default: > + break; > + } > + break; > + default: > + break; > + } > +} > + > +static void sdram_reset(void *opaque) > +{ > + ppc4xx_sdram_t *sdram =3D opaque; > + > + sdram->addr =3D 0; > +} > + > +void ppc440_sdram_init(CPUPPCState *env, int nbanks, > + MemoryRegion *ram_memories, > + hwaddr *ram_bases, hwaddr *ram_sizes, > + int do_init) > +{ > + ppc4xx_sdram_t *sdram; > + > + sdram =3D g_malloc0(sizeof(*sdram)); > + sdram->nbanks =3D nbanks; > + sdram->ram_memories =3D ram_memories; > + memcpy(sdram->ram_bases, ram_bases, nbanks * sizeof(hwaddr)); > + memcpy(sdram->ram_sizes, ram_sizes, nbanks * sizeof(hwaddr)); > + qemu_register_reset(&sdram_reset, sdram); > + ppc_dcr_register(env, SDRAM0_CFGADDR, > + sdram, &dcr_read_sdram, &dcr_write_sdram); > + ppc_dcr_register(env, SDRAM0_CFGDATA, > + sdram, &dcr_read_sdram, &dcr_write_sdram); > + if (do_init) { > + sdram_map_bcr(sdram); > + } > + > + ppc_dcr_register(env, SDRAM_R0BAS, > + sdram, &dcr_read_sdram, &dcr_write_sdram); > + ppc_dcr_register(env, SDRAM_R1BAS, > + sdram, &dcr_read_sdram, &dcr_write_sdram); > + ppc_dcr_register(env, SDRAM_R2BAS, > + sdram, &dcr_read_sdram, &dcr_write_sdram); > + ppc_dcr_register(env, SDRAM_R3BAS, > + sdram, &dcr_read_sdram, &dcr_write_sdram); > + ppc_dcr_register(env, SDRAM_CONF1HB, > + sdram, &dcr_read_sdram, &dcr_write_sdram); > + ppc_dcr_register(env, SDRAM_PLBADDULL, > + sdram, &dcr_read_sdram, &dcr_write_sdram); > + ppc_dcr_register(env, SDRAM_CONF1LL, > + sdram, &dcr_read_sdram, &dcr_write_sdram); > + ppc_dcr_register(env, SDRAM_CONFPATHB, > + sdram, &dcr_read_sdram, &dcr_write_sdram); > + ppc_dcr_register(env, SDRAM_PLBADDUHB, > + sdram, &dcr_read_sdram, &dcr_write_sdram); > +} > + > +/***********************************************************************= ******/ > +/* PLB to AHB bridge */ > +enum { > + AHB_TOP =3D 0xA4, > + AHB_BOT =3D 0xA5, > +}; > + > +typedef struct ppc4xx_ahb_t { > + uint32_t top; > + uint32_t bot; > +} ppc4xx_ahb_t; > + > +static uint32_t dcr_read_ahb(void *opaque, int dcrn) > +{ > + ppc4xx_ahb_t *ahb =3D opaque; > + uint32_t ret =3D 0; > + > + switch (dcrn) { > + case AHB_TOP: > + ret =3D ahb->top; > + break; > + case AHB_BOT: > + ret =3D ahb->bot; > + break; > + default: > + break; > + } > + > + return ret; > +} > + > +static void dcr_write_ahb(void *opaque, int dcrn, uint32_t val) > +{ > + ppc4xx_ahb_t *ahb =3D opaque; > + > + switch (dcrn) { > + case AHB_TOP: > + ahb->top =3D val; > + break; > + case AHB_BOT: > + ahb->bot =3D val; > + break; > + } > +} > + > +static void ppc4xx_ahb_reset(void *opaque) > +{ > + ppc4xx_ahb_t *ahb =3D opaque; > + > + /* No error */ > + ahb->top =3D 0; > + ahb->bot =3D 0; > +} > + > +void ppc4xx_ahb_init(CPUPPCState *env) > +{ > + ppc4xx_ahb_t *ahb; > + > + ahb =3D g_malloc0(sizeof(*ahb)); > + ppc_dcr_register(env, AHB_TOP, ahb, &dcr_read_ahb, &dcr_write_ahb); > + ppc_dcr_register(env, AHB_BOT, ahb, &dcr_read_ahb, &dcr_write_ahb); > + qemu_register_reset(ppc4xx_ahb_reset, ahb); > +} > + > +/***********************************************************************= ******/ > +/* PCI Express controller */ > +/* FIXME: This is not complete and does not work, only implemented parti= ally > + * to allow firmware and guests to find an empty bus. Cards should use P= CI. > + */ > +#include "hw/pci/pcie_host.h" > + > +#define TYPE_PPC460EX_PCIE_HOST "ppc460ex-pcie-host" > +#define PPC460EX_PCIE_HOST(obj) \ > + OBJECT_CHECK(PPC460EXPCIEState, (obj), TYPE_PPC460EX_PCIE_HOST) > + > +typedef struct PPC460EXPCIEState { > + PCIExpressHost host; > + > + MemoryRegion iomem; > + qemu_irq irq[4]; > + int32_t dcrn_base; > + > + uint64_t cfg_base; > + uint32_t cfg_mask; > + uint64_t msg_base; > + uint32_t msg_mask; > + uint64_t omr1_base; > + uint64_t omr1_mask; > + uint64_t omr2_base; > + uint64_t omr2_mask; > + uint64_t omr3_base; > + uint64_t omr3_mask; > + uint64_t reg_base; > + uint32_t reg_mask; > + uint32_t special; > + uint32_t cfg; > +} PPC460EXPCIEState; > + > +#define DCRN_PCIE0_BASE 0x100 > +#define DCRN_PCIE1_BASE 0x120 > + > +enum { > + PEGPL_CFGBAH =3D 0x0, > + PEGPL_CFGBAL, > + PEGPL_CFGMSK, > + PEGPL_MSGBAH, > + PEGPL_MSGBAL, > + PEGPL_MSGMSK, > + PEGPL_OMR1BAH, > + PEGPL_OMR1BAL, > + PEGPL_OMR1MSKH, > + PEGPL_OMR1MSKL, > + PEGPL_OMR2BAH, > + PEGPL_OMR2BAL, > + PEGPL_OMR2MSKH, > + PEGPL_OMR2MSKL, > + PEGPL_OMR3BAH, > + PEGPL_OMR3BAL, > + PEGPL_OMR3MSKH, > + PEGPL_OMR3MSKL, > + PEGPL_REGBAH, > + PEGPL_REGBAL, > + PEGPL_REGMSK, > + PEGPL_SPECIAL, > + PEGPL_CFG, > +}; > + > +static uint32_t dcr_read_pcie(void *opaque, int dcrn) > +{ > + PPC460EXPCIEState *state =3D opaque; > + uint32_t ret =3D 0; > + > + switch (dcrn - state->dcrn_base) { > + case PEGPL_CFGBAH: > + ret =3D state->cfg_base >> 32; > + break; > + case PEGPL_CFGBAL: > + ret =3D state->cfg_base; > + break; > + case PEGPL_CFGMSK: > + ret =3D state->cfg_mask; > + break; > + case PEGPL_MSGBAH: > + ret =3D state->msg_base >> 32; > + break; > + case PEGPL_MSGBAL: > + ret =3D state->msg_base; > + break; > + case PEGPL_MSGMSK: > + ret =3D state->msg_mask; > + break; > + case PEGPL_OMR1BAH: > + ret =3D state->omr1_base >> 32; > + break; > + case PEGPL_OMR1BAL: > + ret =3D state->omr1_base; > + break; > + case PEGPL_OMR1MSKH: > + ret =3D state->omr1_mask >> 32; > + break; > + case PEGPL_OMR1MSKL: > + ret =3D state->omr1_mask; > + break; > + case PEGPL_OMR2BAH: > + ret =3D state->omr2_base >> 32; > + break; > + case PEGPL_OMR2BAL: > + ret =3D state->omr2_base; > + break; > + case PEGPL_OMR2MSKH: > + ret =3D state->omr2_mask >> 32; > + break; > + case PEGPL_OMR2MSKL: > + ret =3D state->omr3_mask; > + break; > + case PEGPL_OMR3BAH: > + ret =3D state->omr3_base >> 32; > + break; > + case PEGPL_OMR3BAL: > + ret =3D state->omr3_base; > + break; > + case PEGPL_OMR3MSKH: > + ret =3D state->omr3_mask >> 32; > + break; > + case PEGPL_OMR3MSKL: > + ret =3D state->omr3_mask; > + break; > + case PEGPL_REGBAH: > + ret =3D state->reg_base >> 32; > + break; > + case PEGPL_REGBAL: > + ret =3D state->reg_base; > + break; > + case PEGPL_REGMSK: > + ret =3D state->reg_mask; > + break; > + case PEGPL_SPECIAL: > + ret =3D state->special; > + break; > + case PEGPL_CFG: > + ret =3D state->cfg; > + break; > + } > + > + return ret; > +} > + > +static void dcr_write_pcie(void *opaque, int dcrn, uint32_t val) > +{ > + PPC460EXPCIEState *s =3D opaque; > + uint64_t size; > + > + switch (dcrn - s->dcrn_base) { > + case PEGPL_CFGBAH: > + s->cfg_base =3D ((uint64_t)val << 32) | (s->cfg_base & 0xfffffff= f); > + break; > + case PEGPL_CFGBAL: > + s->cfg_base =3D (s->cfg_base & 0xffffffff00000000ULL) | val; > + break; > + case PEGPL_CFGMSK: > + s->cfg_mask =3D val; > + size =3D ~(val & 0xfffffffe) + 1; > + qemu_mutex_lock_iothread(); > + pcie_host_mmcfg_update(PCIE_HOST_BRIDGE(s), val & 1, s->cfg_base= , size); > + qemu_mutex_unlock_iothread(); > + break; > + case PEGPL_MSGBAH: > + s->msg_base =3D ((uint64_t)val << 32) | (s->msg_base & 0xfffffff= f); > + break; > + case PEGPL_MSGBAL: > + s->msg_base =3D (s->msg_base & 0xffffffff00000000ULL) | val; > + break; > + case PEGPL_MSGMSK: > + s->msg_mask =3D val; > + break; > + case PEGPL_OMR1BAH: > + s->omr1_base =3D ((uint64_t)val << 32) | (s->omr1_base & 0xfffff= fff); > + break; > + case PEGPL_OMR1BAL: > + s->omr1_base =3D (s->omr1_base & 0xffffffff00000000ULL) | val; > + break; > + case PEGPL_OMR1MSKH: > + s->omr1_mask =3D ((uint64_t)val << 32) | (s->omr1_mask & 0xfffff= fff); > + break; > + case PEGPL_OMR1MSKL: > + s->omr1_mask =3D (s->omr1_mask & 0xffffffff00000000ULL) | val; > + break; > + case PEGPL_OMR2BAH: > + s->omr2_base =3D ((uint64_t)val << 32) | (s->omr2_base & 0xfffff= fff); > + break; > + case PEGPL_OMR2BAL: > + s->omr2_base =3D (s->omr2_base & 0xffffffff00000000ULL) | val; > + break; > + case PEGPL_OMR2MSKH: > + s->omr2_mask =3D ((uint64_t)val << 32) | (s->omr2_mask & 0xfffff= fff); > + break; > + case PEGPL_OMR2MSKL: > + s->omr2_mask =3D (s->omr2_mask & 0xffffffff00000000ULL) | val; > + break; > + case PEGPL_OMR3BAH: > + s->omr3_base =3D ((uint64_t)val << 32) | (s->omr3_base & 0xfffff= fff); > + break; > + case PEGPL_OMR3BAL: > + s->omr3_base =3D (s->omr3_base & 0xffffffff00000000ULL) | val; > + break; > + case PEGPL_OMR3MSKH: > + s->omr3_mask =3D ((uint64_t)val << 32) | (s->omr3_mask & 0xfffff= fff); > + break; > + case PEGPL_OMR3MSKL: > + s->omr3_mask =3D (s->omr3_mask & 0xffffffff00000000ULL) | val; > + break; > + case PEGPL_REGBAH: > + s->reg_base =3D ((uint64_t)val << 32) | (s->reg_base & 0xfffffff= f); > + break; > + case PEGPL_REGBAL: > + s->reg_base =3D (s->reg_base & 0xffffffff00000000ULL) | val; > + break; > + case PEGPL_REGMSK: > + s->reg_mask =3D val; > + /* FIXME: how is size encoded? */ > + size =3D (val =3D=3D 0x7001 ? 4096 : ~(val & 0xfffffffe) + 1); > + break; > + case PEGPL_SPECIAL: > + s->special =3D val; > + break; > + case PEGPL_CFG: > + s->cfg =3D val; > + break; > + } > +} > + > +static void ppc460ex_set_irq(void *opaque, int irq_num, int level) > +{ > + PPC460EXPCIEState *s =3D opaque; > + qemu_set_irq(s->irq[irq_num], level); > +} > + > +static void ppc460ex_pcie_realize(DeviceState *dev, Error **errp) > +{ > + PPC460EXPCIEState *s =3D PPC460EX_PCIE_HOST(dev); > + PCIHostState *pci =3D PCI_HOST_BRIDGE(dev); > + int i, id; > + char buf[16]; > + > + switch (s->dcrn_base) { > + case DCRN_PCIE0_BASE: > + id =3D 0; > + break; > + case DCRN_PCIE1_BASE: > + id =3D 1; > + break; > + } > + snprintf(buf, sizeof(buf), "pcie%d-io", id); > + memory_region_init(&s->iomem, OBJECT(s), buf, UINT64_MAX); > + for (i =3D 0; i < 4; i++) { > + sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); > + } > + snprintf(buf, sizeof(buf), "pcie.%d", id); > + pci->bus =3D pci_register_root_bus(DEVICE(s), buf, ppc460ex_set_irq, > + pci_swizzle_map_irq_fn, s, &s->iomem, > + get_system_io(), 0, 4, TYPE_PCIE_BUS); > +} > + > +static Property ppc460ex_pcie_props[] =3D { > + DEFINE_PROP_INT32("dcrn-base", PPC460EXPCIEState, dcrn_base, -1), > + DEFINE_PROP_END_OF_LIST(), > +}; > + > +static void ppc460ex_pcie_class_init(ObjectClass *klass, void *data) > +{ > + DeviceClass *dc =3D DEVICE_CLASS(klass); > + > + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); > + dc->realize =3D ppc460ex_pcie_realize; > + dc->props =3D ppc460ex_pcie_props; > + dc->hotpluggable =3D false; > +} > + > +static const TypeInfo ppc460ex_pcie_host_info =3D { > + .name =3D TYPE_PPC460EX_PCIE_HOST, > + .parent =3D TYPE_PCIE_HOST_BRIDGE, > + .instance_size =3D sizeof(PPC460EXPCIEState), > + .class_init =3D ppc460ex_pcie_class_init, > +}; > + > +static void ppc460ex_pcie_register(void) > +{ > + type_register_static(&ppc460ex_pcie_host_info); > +} > + > +type_init(ppc460ex_pcie_register) > + > +static void ppc460ex_pcie_register_dcrs(PPC460EXPCIEState *s, CPUPPCStat= e *env) > +{ > + ppc_dcr_register(env, s->dcrn_base + PEGPL_CFGBAH, s, > + &dcr_read_pcie, &dcr_write_pcie); > + ppc_dcr_register(env, s->dcrn_base + PEGPL_CFGBAL, s, > + &dcr_read_pcie, &dcr_write_pcie); > + ppc_dcr_register(env, s->dcrn_base + PEGPL_CFGMSK, s, > + &dcr_read_pcie, &dcr_write_pcie); > + ppc_dcr_register(env, s->dcrn_base + PEGPL_MSGBAH, s, > + &dcr_read_pcie, &dcr_write_pcie); > + ppc_dcr_register(env, s->dcrn_base + PEGPL_MSGBAL, s, > + &dcr_read_pcie, &dcr_write_pcie); > + ppc_dcr_register(env, s->dcrn_base + PEGPL_MSGMSK, s, > + &dcr_read_pcie, &dcr_write_pcie); > + ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1BAH, s, > + &dcr_read_pcie, &dcr_write_pcie); > + ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1BAL, s, > + &dcr_read_pcie, &dcr_write_pcie); > + ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1MSKH, s, > + &dcr_read_pcie, &dcr_write_pcie); > + ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1MSKL, s, > + &dcr_read_pcie, &dcr_write_pcie); > + ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2BAH, s, > + &dcr_read_pcie, &dcr_write_pcie); > + ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2BAL, s, > + &dcr_read_pcie, &dcr_write_pcie); > + ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2MSKH, s, > + &dcr_read_pcie, &dcr_write_pcie); > + ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2MSKL, s, > + &dcr_read_pcie, &dcr_write_pcie); > + ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3BAH, s, > + &dcr_read_pcie, &dcr_write_pcie); > + ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3BAL, s, > + &dcr_read_pcie, &dcr_write_pcie); > + ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3MSKH, s, > + &dcr_read_pcie, &dcr_write_pcie); > + ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3MSKL, s, > + &dcr_read_pcie, &dcr_write_pcie); > + ppc_dcr_register(env, s->dcrn_base + PEGPL_REGBAH, s, > + &dcr_read_pcie, &dcr_write_pcie); > + ppc_dcr_register(env, s->dcrn_base + PEGPL_REGBAL, s, > + &dcr_read_pcie, &dcr_write_pcie); > + ppc_dcr_register(env, s->dcrn_base + PEGPL_REGMSK, s, > + &dcr_read_pcie, &dcr_write_pcie); > + ppc_dcr_register(env, s->dcrn_base + PEGPL_SPECIAL, s, > + &dcr_read_pcie, &dcr_write_pcie); > + ppc_dcr_register(env, s->dcrn_base + PEGPL_CFG, s, > + &dcr_read_pcie, &dcr_write_pcie); > +} > + > +void ppc460ex_pcie_init(CPUPPCState *env) > +{ > + DeviceState *dev; > + > + dev =3D qdev_create(NULL, TYPE_PPC460EX_PCIE_HOST); > + qdev_prop_set_int32(dev, "dcrn-base", DCRN_PCIE0_BASE); > + qdev_init_nofail(dev); > + object_property_set_bool(OBJECT(dev), true, "realized", NULL); > + ppc460ex_pcie_register_dcrs(PPC460EX_PCIE_HOST(dev), env); > + > + dev =3D qdev_create(NULL, TYPE_PPC460EX_PCIE_HOST); > + qdev_prop_set_int32(dev, "dcrn-base", DCRN_PCIE1_BASE); > + qdev_init_nofail(dev); > + object_property_set_bool(OBJECT(dev), true, "realized", NULL); > + ppc460ex_pcie_register_dcrs(PPC460EX_PCIE_HOST(dev), env); > +} > diff --git a/include/hw/pci/pcie_host.h b/include/hw/pci/pcie_host.h > index 4d23c80..3f7b988 100644 > --- a/include/hw/pci/pcie_host.h > +++ b/include/hw/pci/pcie_host.h > @@ -65,7 +65,7 @@ void pcie_host_mmcfg_update(PCIExpressHost *e, > * bit 12 - 14: function number > * bit 0 - 11: offset in configuration space of a given device > */ > -#define PCIE_MMCFG_SIZE_MAX (1ULL << 28) > +#define PCIE_MMCFG_SIZE_MAX (1ULL << 29) > #define PCIE_MMCFG_SIZE_MIN (1ULL << 20) > #define PCIE_MMCFG_BUS_BIT 20 > #define PCIE_MMCFG_BUS_MASK 0x1ff --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson --eRtJSFbw+EEWtPj3 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAEBCAAdFiEEdfRlhq5hpmzETofcbDjKyiDZs5IFAlqGSrMACgkQbDjKyiDZ s5LmDRAAsIj+hHkQC/4nqM5KehhHOx/lS2HsfMiuVNHrq3pbQuwQnvJSwKpwcGe4 FIXs4bLiFwY+Ox377MHCvD4A3eddJm6uy4587qI0ZANIRRXSMPsO6O7cRlLBZ+zF GTiUIC/mkQW/dZySFrm3wSFV+5j4Qe538/STXWCRjBMzQsL5m/9F4ZTbIl5RgOqO iPtPTSm0UG8OyO0flRPkWsp5LbQJTI06VaYCPL9futiWo/EI7xjFj15JYEnQ9mI6 1u37O6ITmA7deec5wgPwzprmDSDdia0wY//mWztaxfI2AmRLfa/3LWfbkxJRhxHj P4Mz1r5ECfTK0y7uwsg6jG0VJBvkWTF9PhelKFwVAd+FYmzT0/qUZCXysc7pqOQN u7sZ5SGXpiE5nrJFI3M8oZ+1jcPoSCWd7NnCJdDa+oDjwaTrquEnzy7k2FClbP4h 6Qft9PLxy0L6spnc2UcnayUVYLia6kHn7Nf4JWCVFm/X35GH2Pr4OwmgNeZKAJin x75Dw1Cyy7rFu5NsC8BbOPp8t1itMEyvhel/a/oUlafDC4BCQVf2iN9QEAy5rUVM BixfzWyqpvdblaj6ngwr5+cAj2y+6ho4WxPf6mJeAk3ZmB8s7+ZDZakYvcOtkoGg MBP61z2q8HTdC0ZehaVWtVhWPKh55VonXi2sr4rRLyhUczZZxXg= =95ia -----END PGP SIGNATURE----- --eRtJSFbw+EEWtPj3--