Return-Path: Received: from mail-bn3nam01on0102.outbound.protection.outlook.com ([104.47.33.102]:13054 "EHLO NAM01-BN3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1755212AbeCHE5I (ORCPT ); Wed, 7 Mar 2018 23:57:08 -0500 From: Sasha Levin To: "linux-kernel@vger.kernel.org" , "stable@vger.kernel.org" CC: Jerome Brunet , "David S . Miller" , Sasha Levin Subject: [PATCH AUTOSEL for 4.15 36/78] net: phy: meson-gxl: check phy_write return value Date: Thu, 8 Mar 2018 04:56:17 +0000 Message-ID: <20180308045525.7662-36-alexander.levin@microsoft.com> References: <20180308045525.7662-1-alexander.levin@microsoft.com> In-Reply-To: <20180308045525.7662-1-alexander.levin@microsoft.com> Content-Language: en-US Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org List-ID: From: Jerome Brunet [ Upstream commit 9042b46eda33ef5db3cdfc9e12b3c8cabb196141 ] Always check phy_write return values. Better to be safe than sorry Reviewed-by: Andrew Lunn Signed-off-by: Jerome Brunet Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/phy/meson-gxl.c | 50 ++++++++++++++++++++++++++++++++++-------= ---- 1 file changed, 38 insertions(+), 12 deletions(-) diff --git a/drivers/net/phy/meson-gxl.c b/drivers/net/phy/meson-gxl.c index 842eb871a6e3..f431c83ba0b5 100644 --- a/drivers/net/phy/meson-gxl.c +++ b/drivers/net/phy/meson-gxl.c @@ -26,27 +26,53 @@ =20 static int meson_gxl_config_init(struct phy_device *phydev) { + int ret; + /* Enable Analog and DSP register Bank access by */ - phy_write(phydev, 0x14, 0x0000); - phy_write(phydev, 0x14, 0x0400); - phy_write(phydev, 0x14, 0x0000); - phy_write(phydev, 0x14, 0x0400); + ret =3D phy_write(phydev, 0x14, 0x0000); + if (ret) + return ret; + ret =3D phy_write(phydev, 0x14, 0x0400); + if (ret) + return ret; + ret =3D phy_write(phydev, 0x14, 0x0000); + if (ret) + return ret; + ret =3D phy_write(phydev, 0x14, 0x0400); + if (ret) + return ret; =20 /* Write Analog register 23 */ - phy_write(phydev, 0x17, 0x8E0D); - phy_write(phydev, 0x14, 0x4417); + ret =3D phy_write(phydev, 0x17, 0x8E0D); + if (ret) + return ret; + ret =3D phy_write(phydev, 0x14, 0x4417); + if (ret) + return ret; =20 /* Enable fractional PLL */ - phy_write(phydev, 0x17, 0x0005); - phy_write(phydev, 0x14, 0x5C1B); + ret =3D phy_write(phydev, 0x17, 0x0005); + if (ret) + return ret; + ret =3D phy_write(phydev, 0x14, 0x5C1B); + if (ret) + return ret; =20 /* Program fraction FR_PLL_DIV1 */ - phy_write(phydev, 0x17, 0x029A); - phy_write(phydev, 0x14, 0x5C1D); + ret =3D phy_write(phydev, 0x17, 0x029A); + if (ret) + return ret; + ret =3D phy_write(phydev, 0x14, 0x5C1D); + if (ret) + return ret; =20 /* Program fraction FR_PLL_DIV1 */ - phy_write(phydev, 0x17, 0xAAAA); - phy_write(phydev, 0x14, 0x5C1C); + ret =3D phy_write(phydev, 0x17, 0xAAAA); + if (ret) + return ret; + ret =3D phy_write(phydev, 0x14, 0x5C1C); + if (ret) + return ret; =20 return 0; } --=20 2.14.1