Return-path: Received: from userp2120.oracle.com ([156.151.31.85]) by Galois.linutronix.de with esmtps (TLS1.2:RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1fBqp8-00061Z-RQ for speck@linutronix.de; Fri, 27 Apr 2018 02:01:15 +0200 Received: from pps.filterd (userp2120.oracle.com [127.0.0.1]) by userp2120.oracle.com (8.16.0.22/8.16.0.22) with SMTP id w3QNvvhK040717 for ; Fri, 27 Apr 2018 00:01:08 GMT Received: from aserv0022.oracle.com (aserv0022.oracle.com [141.146.126.234]) by userp2120.oracle.com with ESMTP id 2hfwy9wbd0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Fri, 27 Apr 2018 00:01:08 +0000 Received: from userv0121.oracle.com (userv0121.oracle.com [156.151.31.72]) by aserv0022.oracle.com (8.14.4/8.14.4) with ESMTP id w3R014bs022417 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Fri, 27 Apr 2018 00:01:07 GMT Received: from abhmp0004.oracle.com (abhmp0004.oracle.com [141.146.116.10]) by userv0121.oracle.com (8.14.4/8.13.8) with ESMTP id w3R013A0002993 for ; Fri, 27 Apr 2018 00:01:03 GMT Message-Id: <20180426234831.595082875@localhost.localdomain> Date: Thu, 26 Apr 2018 19:48:28 -0400 From: konrad.wilk@oracle.com Subject: [MODERATED] [PATCH v6 08/11] [PATCH v6 08/10] Linux Patch #8 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: speck@linutronix.de List-ID: Intel and AMD SPEC_CTRL (0x48) MSR semantics may differ in the future (or in fact use different MSRs for the same functionality). As such we need a run-time way to whitelist the appropriate MSR values. Signed-off-by: Konrad Rzeszutek Wilk --- v5: New patch v6: static! Changed the comment to describe the variable better. --- arch/x86/kernel/cpu/bugs.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 0cda27398a73..e7338b04770f 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -35,6 +35,11 @@ static void __init ssb_select_mitigation(void); */ static u64 __read_mostly x86_spec_ctrl_base; +/* + * Allowed per-vendor SPEC_CTRL MSR bits. + */ +static u64 __read_mostly x86_spec_ctrl_mask = ~(SPEC_CTRL_IBRS); + void __init check_bugs(void) { /* @@ -122,7 +127,7 @@ static enum spectre_v2_mitigation spectre_v2_enabled = SPECTRE_V2_NONE; void x86_set_spec_ctrl(u64 val) { - if (val & ~(SPEC_CTRL_IBRS | SPEC_CTRL_RDS)) + if (val & x86_spec_ctrl_mask) WARN_ONCE(1, "SPEC_CTRL MSR value 0x%16llx is unknown.\n", val); else wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base | val); @@ -469,8 +474,10 @@ static void __init ssb_select_mitigation(void) /* * Intel uses the SPEC CTRL MSR Bit(2) for this. */ - if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) + if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) { x86_spec_ctrl_base |= SPEC_CTRL_RDS; + x86_spec_ctrl_mask &= ~(SPEC_CTRL_RDS); + } } } -- 2.14.3