Return-path: Received: from userp2130.oracle.com ([156.151.31.86]) by Galois.linutronix.de with esmtps (TLS1.2:RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1fDKpd-00084q-GW for speck@linutronix.de; Tue, 01 May 2018 04:15:55 +0200 Received: from pps.filterd (userp2130.oracle.com [127.0.0.1]) by userp2130.oracle.com (8.16.0.22/8.16.0.22) with SMTP id w412Afpn109969 for ; Tue, 1 May 2018 02:15:46 GMT Received: from aserv0021.oracle.com (aserv0021.oracle.com [141.146.126.233]) by userp2130.oracle.com with ESMTP id 2hmgdjecr7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Tue, 01 May 2018 02:15:46 +0000 Received: from aserv0122.oracle.com (aserv0122.oracle.com [141.146.126.236]) by aserv0021.oracle.com (8.14.4/8.14.4) with ESMTP id w412Fjoo013562 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Tue, 1 May 2018 02:15:45 GMT Received: from abhmp0015.oracle.com (abhmp0015.oracle.com [141.146.116.21]) by aserv0122.oracle.com (8.14.4/8.14.4) with ESMTP id w412Fj2D024716 for ; Tue, 1 May 2018 02:15:45 GMT Date: Mon, 30 Apr 2018 22:15:31 -0400 From: Konrad Rzeszutek Wilk Subject: [MODERATED] Re: [patch V8 09/15] SSB 9 Message-ID: <20180501021531.GA3241@localhost.localdomain> References: <20180430150423.180110059@linutronix.de> <20180430151232.528270696@linutronix.de> <5ae99b98-2837-edc1-90e3-9e553765d1d4@linux.intel.com> MIME-Version: 1.0 In-Reply-To: <5ae99b98-2837-edc1-90e3-9e553765d1d4@linux.intel.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: speck@linutronix.de List-ID: On Mon, Apr 30, 2018 at 06:25:52PM -0700, speck for Tim Chen wrote: > On 04/30/2018 08:04 AM, speck for Thomas Gleixner wrote: > > > > > void x86_set_spec_ctrl(u64 val) > > { > >- if (val & ~(SPEC_CTRL_IBRS | SPEC_CTRL_RDS)) > >+ if (val & x86_spec_ctrl_mask) > > WARN_ONCE(1, "SPEC_CTRL MSR value 0x%16llx is unknown.\n", val); > > else > > wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base | val); > >@@ -459,6 +465,7 @@ static enum ssb_mitigation_cmd __init __ > > switch (boot_cpu_data.x86_vendor) { > > case X86_VENDOR_INTEL: > > x86_spec_ctrl_base |= SPEC_CTRL_RDS; > >+ x86_spec_ctrl_mask &= ~(SPEC_CTRL_RDS); > > x86_set_spec_ctrl(SPEC_CTRL_RDS); > > We only have cpu 0's RDS set when we ask for SSB to be turned off for whole system > in current v8 patchset. > > I noticed that the x86_set_spec_ctrl call in > init_intel got dropped in current patchset. It was in Konrad's original patchset. Hm, does see x86_setup_ap_spec_ctrl not get called from identify_secondary_cpu? Granted I recall seeing a patch from Thomas on LKML about a regression of X86_FEATURE_IBRS being cleared on AP processors - perhaps that is exatly what you are hitting? What happens if you change the check from X86_FEATURE_IBRS to X86_FEATURE_SPEC_STORE_BYPASS_DISABLE in x86_setup_ap_spec_ctrl?