From: Andes Date: Wed, 30 May 2018 16:36:30 +0800 Subject: [U-Boot] [PATCH] travis.yml: Support RISC-V 64-bit Message-ID: <20180530083630.361-1-uboot@andestech.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: Rick Chen Fix riscv: ax25-ae350 build fail problem https://travis-ci.org/trini/u-boot/jobs/385147373 ... Building current source for 1 boards (1 thread, 2 jobs per thread) riscv: + ax25-ae350 +arch/riscv/cpu/ax25/start.S: Assembler messages: +arch/riscv/cpu/ax25/start.S:48: Error: unrecognized opcode `sd a2,0(t0)' +arch/riscv/cpu/ax25/start.S:112: Error: unrecognized opcode `ld t5,0(t0)' ... After apply the commit configs: ax25-ae350: Set 64-bit as default configuration Toolchain shall be also setuped with 64-bit in .travis.yml. Signed-off-by: Rick Chen Signed-off-by: Rick Chen Reviewed-by: Chih-Mao Chen Cc: Greentime Hu --- .travis.yml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/.travis.yml b/.travis.yml index 937f028..7e90bc9 100644 --- a/.travis.yml +++ b/.travis.yml @@ -87,9 +87,9 @@ before_script: fi - if [[ "${TOOLCHAIN}" == "powerpc" ]]; then ./tools/buildman/buildman --fetch-arch powerpc; fi - if [[ "${TOOLCHAIN}" == "riscv" ]]; then - wget https://github.com/PkmX/riscv-prebuilt-toolchains/releases/download/20180111/riscv32-unknown-elf-toolchain.tar.gz && - tar -C /tmp -xf riscv32-unknown-elf-toolchain.tar.gz && - echo -e "\n[toolchain-prefix]\nriscv = /tmp/riscv32-unknown-elf/bin/riscv32-unknown-elf-" >> ~/.buildman; + wget https://github.com/andestech/prebuilt/releases/download/20180530/riscv64-unknown-linux-gnu.tar.gz && + tar -C /tmp -xf riscv64-unknown-linux-gnu.tar.gz && + echo -e "\n[toolchain-prefix]\nriscv = /tmp/riscv64-unknown-linux-gnu/bin/riscv64-unknown-linux-gnu-" >> ~/.buildman; fi - if [[ "${QEMU_TARGET}" != "" ]]; then git clone git://git.qemu.org/qemu.git /tmp/qemu; -- 2.7.4