From: Jagan Teki Date: Mon, 16 Jul 2018 16:58:34 +0530 Subject: [U-Boot] [RFC 19/35] clk: sunxi: Add initial CLK driver for A10/A20 In-Reply-To: <20180716112850.3961-1-jagan@amarulasolutions.com> References: <20180716112850.3961-1-jagan@amarulasolutions.com> Message-ID: <20180716112850.3961-20-jagan@amarulasolutions.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Add initial clock driver Allwinner for A10/A20. Implemented clock enable and disable functions for USB OHCI, EHCI, OTG and PHY gate and clock registers. Signed-off-by: Jagan Teki --- drivers/clk/sunxi/Kconfig | 7 +++ drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk_a10.c | 105 ++++++++++++++++++++++++++++++++++++ 3 files changed, 113 insertions(+) create mode 100644 drivers/clk/sunxi/clk_a10.c diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig index 065cadf2fe..36acfa1b88 100644 --- a/drivers/clk/sunxi/Kconfig +++ b/drivers/clk/sunxi/Kconfig @@ -8,6 +8,13 @@ config CLK_SUNXI if CLK_SUNXI +config CLK_SUN4I_A10 + bool "Clock driver for Allwinner A10/A20" + default MACH_SUN4I || MACH_SUN7I + help + This enables common clock driver support for platforms based + on Allwinner A10/A20 SoC. + config CLK_SUN8I_H3 bool "Clock driver for Allwinner H3/H5" default MACH_SUNXI_H3_H5 diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile index 37e6bcb147..bcf2c4269d 100644 --- a/drivers/clk/sunxi/Makefile +++ b/drivers/clk/sunxi/Makefile @@ -6,5 +6,6 @@ obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o +obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c new file mode 100644 index 0000000000..1d38d9e28e --- /dev/null +++ b/drivers/clk/sunxi/clk_a10.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Amarula Solutions B.V. + * Author: Jagan Teki + */ + +#include +#include +#include +#include +#include +#include +#include + +struct a10_clk_priv { + void *base; +}; + +static int a10_clk_enable(struct clk *clk) +{ + struct a10_clk_priv *priv = dev_get_priv(clk->dev); + + debug("%s(#%ld)\n", __func__, clk->id); + + switch (clk->id) { + case CLK_AHB_OTG: + case CLK_AHB_EHCI0: + case CLK_AHB_OHCI0: + case CLK_AHB_EHCI1: + case CLK_AHB_OHCI1: + setbits_le32(priv->base + 0x60, BIT(clk->id - CLK_AHB_OTG)); + return 0; + case CLK_USB_OHCI0: + case CLK_USB_OHCI1: + case CLK_USB_PHY: + setbits_le32(priv->base + 0xcc, + BIT(6 + (clk->id - CLK_USB_OHCI0))); + return 0; + default: + debug("%s (CLK#%ld) unhandled\n", __func__, clk->id); + return -ENODEV; + } +} + +static int a10_clk_disable(struct clk *clk) +{ + struct a10_clk_priv *priv = dev_get_priv(clk->dev); + + debug("%s(#%ld)\n", __func__, clk->id); + + switch (clk->id) { + case CLK_AHB_OTG: + case CLK_AHB_EHCI0: + case CLK_AHB_OHCI0: + case CLK_AHB_EHCI1: + case CLK_AHB_OHCI1: + clrbits_le32(priv->base + 0x60, BIT(clk->id - CLK_AHB_OTG)); + return 0; + case CLK_USB_OHCI0: + case CLK_USB_OHCI1: + case CLK_USB_PHY: + clrbits_le32(priv->base + 0xcc, + BIT(6 + (clk->id - CLK_USB_OHCI0))); + return 0; + default: + debug("%s (CLK#%ld) unhandled\n", __func__, clk->id); + return -ENODEV; + } +} + +static struct clk_ops a10_clk_ops = { + .enable = a10_clk_enable, + .disable = a10_clk_disable, +}; + +static int a10_clk_probe(struct udevice *dev) +{ + return 0; +} + +static int a10_clk_ofdata_to_platdata(struct udevice *dev) +{ + struct a10_clk_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + + return 0; +} + +static const struct udevice_id a10_clk_ids[] = { + { .compatible = "allwinner,sun4i-a10-ccu" }, + { .compatible = "allwinner,sun7i-a20-ccu" }, + { } +}; + +U_BOOT_DRIVER(clk_sun4i_a10) = { + .name = "sun4i_a10_ccu", + .id = UCLASS_CLK, + .of_match = a10_clk_ids, + .priv_auto_alloc_size = sizeof(struct a10_clk_priv), + .ofdata_to_platdata = a10_clk_ofdata_to_platdata, + .ops = &a10_clk_ops, + .probe = a10_clk_probe, + .bind = sunxi_clk_bind, +}; -- 2.17.1