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Date: Sat, 11 Aug 2018 13:50:42 +0200
From: Greg KH <greg@kroah.com>
To: Max Filippov <jcmvbkbc@gmail.com>
Cc: stable@vger.kernel.org
Subject: Re: [PATCH] xtensa: increase ranges in ___invalidate_{i,d}cache_all
Message-ID: <20180811115042.GB444@kroah.com>
References: <20180811074423.4169-1-jcmvbkbc@gmail.com>
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On Sat, Aug 11, 2018 at 12:44:23AM -0700, Max Filippov wrote:
> Cache invalidation macros use cache line size to iterate over
> invalidated cache lines, assuming that all cache ways are invalidated by
> single instruction, but xtensa ISA recommends to not assume that for
> future compatibility:
>   In some implementations all ways at index Addry-1..z are invalidated
>   regardless of the specified way, but for future compatibility this
>   behavior should not be assumed.
> 
> Iterate over all cache ways in ___invalidate_icache_all and
> ___invalidate_dcache_all.
> 
> Cc: stable@vger.kernel.org
> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
> ---
>  arch/xtensa/include/asm/cacheasm.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 

<formletter>

This is not the correct way to submit patches for inclusion in the
stable kernel tree.  Please read:
    https://www.kernel.org/doc/html/latest/process/stable-kernel-rules.html
for how to do this properly.

</formletter>