From: Eric Anholt Subject: [PATCH 1/6] drm/v3d: Document cache flushing ABI. Date: Fri, 30 Nov 2018 16:57:54 -0800 Message-ID: <20181201005759.28093-1-eric@anholt.net> Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Return-path: Sender: linux-kernel-owner@vger.kernel.org To: dri-devel@lists.freedesktop.org Cc: linux-kernel@vger.kernel.org, Dave Emett , Thomas Spurden , Eric Anholt List-Id: dri-devel@lists.freedesktop.org Right now, userspace doesn't do any L2T writes, but we should lay out our expectations for how it works. Signed-off-by: Eric Anholt --- include/uapi/drm/v3d_drm.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/uapi/drm/v3d_drm.h b/include/uapi/drm/v3d_drm.h index 35c7d813c66e..95b8f8e82ea5 100644 --- a/include/uapi/drm/v3d_drm.h +++ b/include/uapi/drm/v3d_drm.h @@ -52,6 +52,13 @@ extern "C" { * * This asks the kernel to have the GPU execute an optional binner * command list, and a render command list. + * + * The caches (L1T, slice, and L2T) will be flushed before the job + * executes. The TLB writes are guaranteed to have been flushed by + * the time the render done IRQ happens, which is the trigger for + * out_sync. Any dirtying of cachelines by the job (only possible + * using TMU writes) must be flushed by the caller using the CL's + * cache flush commands. */ struct drm_v3d_submit_cl { /* Pointer to the binner command list. -- 2.20.0.rc1