From: Stefan Agner Date: Tue, 4 Dec 2018 11:10:18 +0100 Subject: [U-Boot] [PATCH v1 1/4] toradex: colibri_vf: fix memory initialization In-Reply-To: <20181204101021.22817-1-stefan@agner.ch> References: <20181204101021.22817-1-stefan@agner.ch> Message-ID: <20181204101021.22817-2-stefan@agner.ch> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: Stefan Agner Commit 3f353ceccbbb ("vf610: refactor DDRMC code") changed on-die termination (ODT) values from 120 Ohm to 60 Ohm and enabled a static read/write leveling which has not been tested with this board. This commit reverts both changes and makes sure that memory gets initialized as it has been done before the mentioned commit. Fixes: 3f353ceccbbb ("vf610: refactor DDRMC code") Signed-off-by: Stefan Agner Acked-by: Max Krummenacher --- board/toradex/colibri_vf/colibri_vf.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c index 4db1757469..19cf748c5d 100644 --- a/board/toradex/colibri_vf/colibri_vf.c +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -42,14 +42,6 @@ DECLARE_GLOBAL_DATA_PTR; #define USB_CDET_GPIO 102 static struct ddrmc_cr_setting colibri_vf_cr_settings[] = { - /* levelling */ - { DDRMC_CR97_WRLVL_EN, 97 }, - { DDRMC_CR98_WRLVL_DL_0(0), 98 }, - { DDRMC_CR99_WRLVL_DL_1(0), 99 }, - { DDRMC_CR102_RDLVL_REG_EN | DDRMC_CR102_RDLVL_GT_REGEN, 102 }, - { DDRMC_CR105_RDLVL_DL_0(0), 105 }, - { DDRMC_CR106_RDLVL_GTDL_0(4), 106 }, - { DDRMC_CR110_RDLVL_DL_1(0) | DDRMC_CR110_RDLVL_GTDL_1(4), 110 }, /* AXI */ { DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 }, { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 }, @@ -88,7 +80,7 @@ static struct ddrmc_cr_setting colibri_vf_cr_settings[] = { DDRMC_CR154_PAD_ZQ_MODE(1) | DDRMC_CR154_DDR_SEL_PAD_CONTR(3) | DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 }, - { DDRMC_CR155_PAD_ODT_BYTE1(1) | DDRMC_CR155_PAD_ODT_BYTE0(1), 155 }, + { DDRMC_CR155_PAD_ODT_BYTE1(2) | DDRMC_CR155_PAD_ODT_BYTE0(2), 155 }, { DDRMC_CR158_TWR(6), 158 }, { DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) | DDRMC_CR161_TODTH_WR(2), 161 }, -- 2.19.1