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Date: Fri, 7 Dec 2018 15:52:53 +0000
From: Catalin Marinas <catalin.marinas@arm.com>
To: Will Deacon <will.deacon@arm.com>
Cc: stable@vger.kernel.org, james.morse@arm.com,
        hayashi.kunihiko@socionext.com,
        linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] arm64: hibernate: Avoid sending cross-calling with
 interrupts disabled
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On Fri, Dec 07, 2018 at 12:47:10PM +0000, Will Deacon wrote:
> Since commit 3b8c9f1cdfc50 ("arm64: IPI each CPU after invalidating the
> I-cache for kernel mappings"), a call to flush_icache_range() will use
> an IPI to cross-call other online CPUs so that any stale instructions
> are flushed from their pipelines. This triggers a WARN during the
> hibernation resume path, where flush_icache_range() is called with
> interrupts disabled and is therefore prone to deadlock:
> 
>   | Disabling non-boot CPUs ...
>   | CPU1: shutdown
>   | psci: CPU1 killed.
>   | CPU2: shutdown
>   | psci: CPU2 killed.
>   | CPU3: shutdown
>   | psci: CPU3 killed.
>   | WARNING: CPU: 0 PID: 1 at ../kernel/smp.c:416 smp_call_function_many+0xd4/0x350
>   | Modules linked in:
>   | CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.20.0-rc4 #1
> 
> Since all secondary CPUs have been taken offline prior to invalidating
> the I-cache, there's actually no need for an IPI and we can simply call
> __flush_icache_range() instead.
> 
> Cc: <stable@vger.kernel.org>
> Fixes: 3b8c9f1cdfc50 ("arm64: IPI each CPU after invalidating the I-cache for kernel mappings")
> Reported-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> Tested-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> Tested-by: James Morse <james.morse@arm.com>
> Signed-off-by: Will Deacon <will.deacon@arm.com>

Queued for 4.20. Thanks.

-- 
Catalin