From: Dmitry Osipenko Subject: [PATCH v1 5/5] clk: tegra: divider: Mark Memory Controller clock as read-only Date: Fri, 12 Apr 2019 01:02:30 +0300 Message-ID: <20190411220230.21726-6-digetx@gmail.com> References: <20190411220230.21726-1-digetx@gmail.com> Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Return-path: In-Reply-To: <20190411220230.21726-1-digetx@gmail.com> Sender: linux-kernel-owner@vger.kernel.org To: Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Thierry Reding , Jonathan Hunter , Joseph Lo Cc: linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org List-Id: linux-tegra@vger.kernel.org The Memory Controller clock rate can't be simply changed and nothing in kernel need to change the rate, hence let's make the clock read-only. Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-divider.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c index 205fe8ff63f0..f891bbb0d06d 100644 --- a/drivers/clk/tegra/clk-divider.c +++ b/drivers/clk/tegra/clk-divider.c @@ -175,6 +175,7 @@ struct clk *tegra_clk_register_mc(const char *name, const char *parent_name, void __iomem *reg, spinlock_t *lock) { return clk_register_divider_table(NULL, name, parent_name, - CLK_IS_CRITICAL, reg, 16, 1, 0, - mc_div_table, lock); + CLK_IS_CRITICAL | + CLK_DIVIDER_READ_ONLY, + reg, 16, 1, 0, mc_div_table, lock); } -- 2.21.0