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Date:   Thu, 5 Nov 2020 18:22:39 +0200
From:   Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To:     Linus Walleij <linus.walleij@linaro.org>
Cc:     Mika Westerberg <mika.westerberg@linux.intel.com>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
        Jamie McClymont <jamie@kwiius.com>
Subject: Re: [PATCH v1 1/2] pinctrl: intel: Fix 2 kOhm bias which is 833 Ohm
Message-ID: <20201105162239.GY4077@smile.fi.intel.com>
References: <20201014104638.84043-1-andriy.shevchenko@linux.intel.com>
 <CACRpkdb_zWU0a3th4XAiZn65iO=8mAt6mpAEOjz-q32kYKpLZQ@mail.gmail.com>
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On Thu, Nov 05, 2020 at 10:09:45AM +0100, Linus Walleij wrote:
> On Wed, Oct 14, 2020 at 12:46 PM Andy Shevchenko
> <andriy.shevchenko@linux.intel.com> wrote:
> 
> > 2 kOhm bias was never an option in Intel GPIO hardware, the available
> > matrix is:
> >
> >         000     none
> >         001     1 kOhm (if available)
> >         010     5 kOhm
> >         100     20 kOhm
> >
> > As easy to get the 3 resistors are gated separately and according to
> > parallel circuits calculations we may get combinations of the above where
> > the result is always strictly less than minimal resistance. Hence,
> > additional values can be:
> >
> >         011     ~833.3 Ohm
> >         101     ~952.4 Ohm
> >         110     ~4 kOhm
> >         111     ~800 Ohm
> >
> > That said, convert TERM definitions to be the bit masks to reflect the above.
> >
> > While at it, enable the same setting for pull down case.
> >
> > Fixes: 7981c0015af2 ("pinctrl: intel: Add Intel Sunrisepoint pin controller and GPIO support")
> > Cc: Jamie McClymont <jamie@kwiius.com>
> > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> 
> Good research!
> 
> I expect this as part of a pull request for fixes or devel.

for-next, but yes, I don't want to be in hurry of backporting this, better to
test it carefully.

-- 
With Best Regards,
Andy Shevchenko