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McKenney" , Catalin Marinas , Will Deacon , Marc Zyngier , Thomas Gleixner , Joey Gouly , Sami Tolvanen , Julien Thierry , Yuichi Ito , rcu@vger.kernel.org Subject: [PATCHv3 2/4] arm64: entry: distinguish pNMI earlier in el0 interrupt Date: Tue, 16 Nov 2021 16:24:48 +0800 Message-Id: <20211116082450.10357-3-kernelfans@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211116082450.10357-1-kernelfans@gmail.com> References: <20211116082450.10357-1-kernelfans@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: rcu@vger.kernel.org For ease of unifying code, it is helpful to lift nmi_{enter,exit}() housekeeping from gic_handle_nmi() to el0_interrupt(). Because gic_handle_nmi() is called by either el1 interrupt or el0, and the housekeeping has already been done in arch level code when el1 interrupt. Note about the original code, which calls enter_from_user_mode() in pNMI context. Although it is weird to call rcu_eqs_exit() in the pseudo NMI context, it has no problem. This is due to the essentiality of pNMI, a higher priority interrupt but not akin to NMI, which allows a break-in at any time. Signed-off-by: Pingfan Liu Cc: Mark Rutland Cc: Paul E. McKenney Cc: Catalin Marinas Cc: Will Deacon Cc: Marc Zyngier Cc: Thomas Gleixner Cc: Joey Gouly Cc: Sami Tolvanen Cc: Julien Thierry Cc: Yuichi Ito Cc: rcu@vger.kernel.org To: linux-arm-kernel@lists.infradead.org --- arch/arm64/kernel/entry-common.c | 35 ++++++++++++++++++++++++-------- 1 file changed, 27 insertions(+), 8 deletions(-) diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm64/kernel/entry-common.c index 5a1a5dd66d04..afcde43f1b73 100644 --- a/arch/arm64/kernel/entry-common.c +++ b/arch/arm64/kernel/entry-common.c @@ -429,7 +429,7 @@ asmlinkage void noinstr el1h_64_sync_handler(struct pt_regs *regs) } } -static __always_inline void __el1_pnmi(struct pt_regs *regs, +static __always_inline void __pnmi_handler_common(struct pt_regs *regs, void (*handler)(struct pt_regs *)) { arm64_enter_nmi(regs); @@ -437,6 +437,12 @@ static __always_inline void __el1_pnmi(struct pt_regs *regs, arm64_exit_nmi(regs); } +static __always_inline void __el1_pnmi(struct pt_regs *regs, + void (*handler)(struct pt_regs *)) +{ + __pnmi_handler_common(regs, handler); +} + static __always_inline void __el1_irq(struct pt_regs *regs, void (*handler)(struct pt_regs *)) { @@ -673,21 +679,34 @@ asmlinkage void noinstr el0t_64_sync_handler(struct pt_regs *regs) } } -static void noinstr el0_interrupt(struct pt_regs *regs, - void (*handler)(struct pt_regs *)) +static __always_inline void __el0_pnmi(struct pt_regs *regs, + void (*handler)(struct pt_regs *)) +{ + __pnmi_handler_common(regs, handler); +} + +static __always_inline void __el0_irq(struct pt_regs *regs, + void (*handler)(struct pt_regs *)) { enter_from_user_mode(regs); + irq_enter_rcu(); + do_interrupt_handler(regs, handler); + irq_exit_rcu(); + exit_to_user_mode(regs); +} +static void noinstr el0_interrupt(struct pt_regs *regs, + void (*handler)(struct pt_regs *)) +{ write_sysreg(DAIF_PROCCTX_NOIRQ, daif); if (regs->pc & BIT(55)) arm64_apply_bp_hardening(); - irq_enter_rcu(); - do_interrupt_handler(regs, handler); - irq_exit_rcu(); - - exit_to_user_mode(regs); + if (IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) && is_in_pnmi(regs)) + __el0_pnmi(regs, handler); + else + __el0_irq(regs, handler); } static void noinstr __el0_irq_handler_common(struct pt_regs *regs) -- 2.31.1