Content-Type: multipart/mixed; boundary="===============3583960849960658133==" MIME-Version: 1.0 From: kernel test robot To: kbuild-all@lists.01.org Subject: Re: [PATCH] PCI: iproc: Set all 24 bits of PCI class code Date: Wed, 05 Jan 2022 22:16:23 +0800 Message-ID: <202201052225.XMsg2fG3-lkp@intel.com> In-Reply-To: <20220105093552.27542-1-pali@kernel.org> List-Id: --===============3583960849960658133== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Hi "Pali, I love your patch! Yet something to improve: [auto build test ERROR on helgaas-pci/next] [also build test ERROR on v5.16-rc8 next-20220105] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Pali-Roh-r/PCI-iproc-Set-a= ll-24-bits-of-PCI-class-code/20220105-173704 base: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next config: arm-randconfig-c002-20220105 (https://download.01.org/0day-ci/archi= ve/20220105/202201052225.XMsg2fG3-lkp(a)intel.com/config) compiler: arm-linux-gnueabi-gcc (GCC) 11.2.0 reproduce (this is a W=3D1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/= make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/0day-ci/linux/commit/8ef1acfb84c08a0331930f9a6= 0884fdd6d7c5e88 git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Pali-Roh-r/PCI-iproc-Set-all-24-bi= ts-of-PCI-class-code/20220105-173704 git checkout 8ef1acfb84c08a0331930f9a60884fdd6d7c5e88 # save the config file to linux build tree mkdir build_dir COMPILER_INSTALL_PATH=3D$HOME/0day COMPILER=3Dgcc-11.2.0 make.cross= O=3Dbuild_dir ARCH=3Darm SHELL=3D/bin/bash drivers/pci/controller/ If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot All errors (new ones prefixed by >>): drivers/pci/controller/pcie-iproc.c: In function 'iproc_pcie_check_link': >> drivers/pci/controller/pcie-iproc.c:798:18: error: 'PCI_CLASS_BRIDGE_PCI= _NORMAL' undeclared (first use in this function); did you mean 'PCI_CLASS_B= RIDGE_PCMCIA'? 798 | class |=3D PCI_CLASS_BRIDGE_PCI_NORMAL; | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ | PCI_CLASS_BRIDGE_PCMCIA drivers/pci/controller/pcie-iproc.c:798:18: note: each undeclared identi= fier is reported only once for each function it appears in vim +798 drivers/pci/controller/pcie-iproc.c 765 = 766 static int iproc_pcie_check_link(struct iproc_pcie *pcie) 767 { 768 struct device *dev =3D pcie->dev; 769 u32 hdr_type, link_ctrl, link_status, class, val; 770 bool link_is_active =3D false; 771 = 772 /* 773 * PAXC connects to emulated endpoint devices directly and does not 774 * have a Serdes. Therefore skip the link detection logic here. 775 */ 776 if (pcie->ep_is_internal) 777 return 0; 778 = 779 val =3D iproc_pcie_read_reg(pcie, IPROC_PCIE_LINK_STATUS); 780 if (!(val & PCIE_PHYLINKUP) || !(val & PCIE_DL_ACTIVE)) { 781 dev_err(dev, "PHY or data link is INACTIVE!\n"); 782 return -ENODEV; 783 } 784 = 785 /* make sure we are not in EP mode */ 786 iproc_pci_raw_config_read32(pcie, 0, PCI_HEADER_TYPE, 1, &hdr_type); 787 if ((hdr_type & 0x7f) !=3D PCI_HEADER_TYPE_BRIDGE) { 788 dev_err(dev, "in EP mode, hdr=3D%#02x\n", hdr_type); 789 return -EFAULT; 790 } 791 = 792 /* force class to PCI_CLASS_BRIDGE_PCI_NORMAL (0x060400) */ 793 #define PCI_BRIDGE_CTRL_REG_OFFSET 0x43c 794 #define PCI_BRIDGE_CTRL_REG_CLASS_MASK 0xffffff 795 iproc_pci_raw_config_read32(pcie, 0, PCI_BRIDGE_CTRL_REG_OFFSET, 796 4, &class); 797 class &=3D ~PCI_BRIDGE_CTRL_REG_CLASS_MASK; > 798 class |=3D PCI_CLASS_BRIDGE_PCI_NORMAL; 799 iproc_pci_raw_config_write32(pcie, 0, PCI_BRIDGE_CTRL_REG_OFFSET, 800 4, class); 801 = 802 /* check link status to see if link is active */ 803 iproc_pci_raw_config_read32(pcie, 0, IPROC_PCI_EXP_CAP + PCI_EXP_LN= KSTA, 804 2, &link_status); 805 if (link_status & PCI_EXP_LNKSTA_NLW) 806 link_is_active =3D true; 807 = 808 if (!link_is_active) { 809 /* try GEN 1 link speed */ 810 #define PCI_TARGET_LINK_SPEED_MASK 0xf 811 #define PCI_TARGET_LINK_SPEED_GEN2 0x2 812 #define PCI_TARGET_LINK_SPEED_GEN1 0x1 813 iproc_pci_raw_config_read32(pcie, 0, 814 IPROC_PCI_EXP_CAP + PCI_EXP_LNKCTL2, 815 4, &link_ctrl); 816 if ((link_ctrl & PCI_TARGET_LINK_SPEED_MASK) =3D=3D 817 PCI_TARGET_LINK_SPEED_GEN2) { 818 link_ctrl &=3D ~PCI_TARGET_LINK_SPEED_MASK; 819 link_ctrl |=3D PCI_TARGET_LINK_SPEED_GEN1; 820 iproc_pci_raw_config_write32(pcie, 0, 821 IPROC_PCI_EXP_CAP + PCI_EXP_LNKCTL2, 822 4, link_ctrl); 823 msleep(100); 824 = 825 iproc_pci_raw_config_read32(pcie, 0, 826 IPROC_PCI_EXP_CAP + PCI_EXP_LNKSTA, 827 2, &link_status); 828 if (link_status & PCI_EXP_LNKSTA_NLW) 829 link_is_active =3D true; 830 } 831 } 832 = 833 dev_info(dev, "link: %s\n", link_is_active ? "UP" : "DOWN"); 834 = 835 return link_is_active ? 0 : -ENODEV; 836 } 837 = --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org --===============3583960849960658133==--