Content-Type: multipart/mixed; boundary="===============7705258943629384560==" MIME-Version: 1.0 From: Sumit Gupta To: kbuild-all@lists.01.org Subject: [Patch v4 2/9] dt-bindings: arm: tegra: Add NVIDIA Tegra194 CBB1.0 binding Date: Thu, 05 May 2022 22:36:30 +0530 Message-ID: <20220505170637.26538-3-sumitg@nvidia.com> In-Reply-To: <20220505170637.26538-1-sumitg@nvidia.com> List-Id: --===============7705258943629384560== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Add device-tree binding documentation to represent the error handling driver for Control Backbone (CBB) version 1.0 used in Tegra194 SOC. The driver prints debug information about failed transactions due to illegal register accesses on receiving interrupt from CBB. Signed-off-by: Sumit Gupta --- .../arm/tegra/nvidia,tegra194-cbb.yaml | 93 +++++++++++++++++++ 1 file changed, 93 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegr= a194-cbb.yaml diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-cb= b.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-cbb.ya= ml new file mode 100644 index 000000000000..3167f0450298 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-cbb.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: NVIDIA Tegra194 CBB 1.0 device tree bindings + +maintainers: + - Sumit Gupta + +description: |+ + The Control Backbone (CBB) is comprised of the physical path from an ini= tiator to a target's + register configuration space. CBB 1.0 has multiple hierarchical sub-NOCs= (Network-on-Chip) and + connects various initiators and targets using different bridges like AXI= P2P, AXI2APB. + + This driver handles errors due to illegal register accesses reported by = the NOCs inside the CBB. + NOCs reporting errors are cluster NOCs "AON-NOC, SCE-NOC, RCE-NOC, BPMP-= NOC, CV-NOC" and "CBB + Central NOC" which is the main NOC. + + By default, the access issuing initiator is informed about the error usi= ng SError or Data Abort + exception unless the ERD (Error Response Disable) is enabled/set for tha= t initiator. If the ERD + is enabled, then SError or Data Abort is masked and the error is reporte= d with interrupt. + + - For CCPLEX (CPU Complex) initiator, the driver sets ERD bit. So, the e= rrors due to illegal + accesses from CCPLEX are reported by interrupts. If ERD is not set, th= en error is reported by + SError. + - For other initiators, the ERD is disabled. So, the access issuing init= iator is informed about + the illegal access by Data Abort exception. In addition, an interrupt = is also generated to + CCPLEX. These initiators include all engines using Cortex-R5 (which is= ARMv7 CPU cluster) and + engines like TSEC (Security co-processor), NVDEC (NVIDIA Video Decoder= engine) etc which can + initiate transactions. + + The driver prints relevant debug information like Error Code, Error Desc= ription, Master, Address, + AXI ID, Cache, Protection, Security Group etc on receiving error notific= ation. + +properties: + $nodename: + pattern: "^[a-z]+-noc@[0-9a-f]+$" + + compatible: + enum: + - nvidia,tegra194-cbb-noc + - nvidia,tegra194-aon-noc + - nvidia,tegra194-bpmp-noc + - nvidia,tegra194-rce-noc + - nvidia,tegra194-sce-noc + + reg: + maxItems: 1 + + interrupts: + description: + CCPLEX receives secure or nonsecure interrupt depending on error typ= e. A secure interrupt is + received for SEC(firewall) & SLV errors and a non-secure interrupt i= s received for TMO & DEC + errors. + items: + - description: non-secure interrupt + - description: secure interrupt + + nvidia,axi2apb: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: + Specifies the node having all axi2apb bridges which need to be check= ed for any error logged + in their status register. + + nvidia,apbmisc: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: + Specifies the apbmisc node which need to be used for reading ERD reg= ister. + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - nvidia,axi2apb + - nvidia,apbmisc + +examples: + - | + #include + + cbb-noc(a)2300000 { + compatible =3D "nvidia,tegra194-cbb-noc"; + reg =3D <0x02300000 0x1000>; + interrupts =3D , + ; + nvidia,axi2apb =3D <&axi2apb>; + nvidia,apbmisc =3D <&apbmisc>; + status =3D "okay"; + }; -- = 2.17.1 --===============7705258943629384560==--