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From: Sumit Gupta <sumitg@nvidia.com>
To: kbuild-all@lists.01.org
Subject: [Patch v5 4/9] arm64: tegra: Add node for CBB1.0 in Tegra194 SOC
Date: Fri, 06 May 2022 16:42:12 +0530
Message-ID: <20220506111217.8833-5-sumitg@nvidia.com>
In-Reply-To: <20220506111217.8833-1-sumitg@nvidia.com>
List-Id: <oe-kbuild-all.lists.linux.dev>

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Adding device tree nodes to enable the driver for handling errors from
Control Backbone(CBB). CBB version 1.0 is used in Tegra194 SOC.

Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
---
 arch/arm64/boot/dts/nvidia/tegra194.dtsi | 62 +++++++++++++++++++++++-
 1 file changed, 61 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts=
/nvidia/tegra194.dtsi
index d1f8248c00f4..c0da62436ed5 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -23,7 +23,7 @@
 		#size-cells =3D <1>;
 		ranges =3D <0x0 0x0 0x0 0x40000000>;
 =

-		misc(a)100000 {
+		apbmisc: misc(a)100000 {
 			compatible =3D "nvidia,tegra194-misc";
 			reg =3D <0x00100000 0xf000>,
 			      <0x0010f000 0x1000>;
@@ -88,6 +88,27 @@
 			gpio-controller;
 		};
 =

+		cbb-noc(a)2300000 {
+			compatible =3D "nvidia,tegra194-cbb-noc";
+			reg =3D <0x02300000 0x1000>;
+			interrupts =3D <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+			nvidia,axi2apb =3D <&axi2apb>;
+			nvidia,apbmisc =3D <&apbmisc>;
+			status =3D "okay";
+		};
+
+		axi2apb: axi2apb(a)2390000 {
+			compatible =3D "nvidia,tegra194-axi2apb";
+			reg =3D <0x2390000 0x1000>,
+			    <0x23a0000 0x1000>,
+			    <0x23b0000 0x1000>,
+			    <0x23c0000 0x1000>,
+			    <0x23d0000 0x1000>,
+			    <0x23e0000 0x1000>;
+			status =3D "okay";
+		 };
+
 		ethernet(a)2490000 {
 			compatible =3D "nvidia,tegra194-eqos",
 				     "nvidia,tegra186-eqos",
@@ -1460,6 +1481,26 @@
 			#phy-cells =3D <0>;
 		};
 =

+		sce-noc(a)b600000 {
+			compatible =3D "nvidia,tegra194-sce-noc";
+			reg =3D <0xb600000 0x1000>;
+			interrupts =3D <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+			nvidia,axi2apb =3D <&axi2apb>;
+			nvidia,apbmisc =3D <&apbmisc>;
+			status =3D "okay";
+		};
+
+		rce-noc(a)be00000 {
+			compatible =3D "nvidia,tegra194-rce-noc";
+			reg =3D <0xbe00000 0x1000>;
+			interrupts =3D <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+			nvidia,axi2apb =3D <&axi2apb>;
+			nvidia,apbmisc =3D <&apbmisc>;
+			status =3D "okay";
+		};
+
 		hsp_aon: hsp(a)c150000 {
 			compatible =3D "nvidia,tegra194-hsp";
 			reg =3D <0x0c150000 0x90000>;
@@ -1594,6 +1635,25 @@
 =

 		};
 =

+		aon-noc(a)c600000 {
+			compatible =3D "nvidia,tegra194-aon-noc";
+			reg =3D <0xc600000 0x1000>;
+			interrupts =3D <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+			nvidia,apbmisc =3D <&apbmisc>;
+			status =3D "okay";
+		};
+
+		bpmp-noc(a)d600000 {
+			compatible =3D "nvidia,tegra194-bpmp-noc";
+			reg =3D <0xd600000 0x1000>;
+			interrupts =3D <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+			nvidia,axi2apb =3D <&axi2apb>;
+			nvidia,apbmisc =3D <&apbmisc>;
+			status =3D "okay";
+		};
+
 		iommu(a)10000000 {
 			compatible =3D "nvidia,tegra194-smmu", "nvidia,smmu-500";
 			reg =3D <0x10000000 0x800000>;
-- =

2.17.1

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