Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 75C25D51D for ; Wed, 6 Mar 2024 01:23:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.13 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709688198; cv=none; b=MM2hbXuq4+jfEw4B3C7K+vkbceCAJY3+R1gOLwIKKpmvllObKzfQS3rf109BJD8uc9sip/U+TxFk6K0IkhSNXsxBzoyup66WX1nuaAK/RIFZHBm8B4HY8lASHCj7aRHjAWeyO+c6uZ7YrhWFwsL4sdhpICsFYOzBc8HAzaq4ML4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709688198; c=relaxed/simple; bh=55cz6R9p9KOyKnGwg64H3XIpw7VvJls03sCwitIbJko=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=SRbZoi2o1Zk0PCSPiql7NN4fwIKqdivJtdfdsjmV6tQUXZh/BZA2ts+ZSLxigm5aBcHx41F9yniq0YE68iHq4H9m4oecNktcXzjyZj6KDo2YC5mTYqX5xaR8Rr5vG1swL9Rvx03p/yLJ9urBByjlxC/RBAObeROu7Z1Y66Y8kcQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=eyPWHlU3; arc=none smtp.client-ip=198.175.65.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="eyPWHlU3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1709688197; x=1741224197; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=55cz6R9p9KOyKnGwg64H3XIpw7VvJls03sCwitIbJko=; b=eyPWHlU3cFzNZmj+D/tMVPQBIKrqwBP8HEFbUu0AOC9N+tAeTxA5k3PT z6Xicqjox3AGzDJCTK8MQcecJHZLSe4KI6ReJjkE+XPY//cjBVuvCHVGU Fi+kxr5ZnLO7nCBTXuvxzE2NVV9VGpDqvmd9kuS82hHTjuNuRgQVZhxBV xqnv7Dr12cQ8Kem10s4K9y8GiDrosbNwq+AyPdmKQ2w7Unykgavpo/K3w 29Y/SKXlpionEDqNo6igsmREiADuHRwh7OyNnlseQ+ZECDkwoinnL7I6f 7QEPuJkfVQWY7uPiTsgChMcsuqdJ3WRw1RBGbYuzajPBZsWIoTQJePxWK Q==; X-IronPort-AV: E=McAfee;i="6600,9927,11004"; a="15423882" X-IronPort-AV: E=Sophos;i="6.06,207,1705392000"; d="scan'208";a="15423882" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2024 17:23:17 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,207,1705392000"; d="scan'208";a="9651774" Received: from unknown (HELO intel.com) ([10.247.118.75]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2024 17:23:09 -0800 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Joonas Lahtinen , Matt Roper , John Harrison , stable@vger.kernel.org, Andi Shyti , Andi Shyti , Tvrtko Ursulin Subject: [PATCH v4 1/3] drm/i915/gt: Disable HW load balancing for CCS Date: Wed, 6 Mar 2024 02:22:45 +0100 Message-ID: <20240306012247.246003-2-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240306012247.246003-1-andi.shyti@linux.intel.com> References: <20240306012247.246003-1-andi.shyti@linux.intel.com> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The hardware should not dynamically balance the load between CCS engines. Wa_14019159160 recommends disabling it across all platforms. Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement") Signed-off-by: Andi Shyti Cc: Chris Wilson Cc: Joonas Lahtinen Cc: Matt Roper Cc: # v6.2+ --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index 50962cfd1353..cf709f6c05ae 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -1478,6 +1478,7 @@ #define GEN12_RCU_MODE _MMIO(0x14800) #define GEN12_RCU_MODE_CCS_ENABLE REG_BIT(0) +#define XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE REG_BIT(1) #define CHV_FUSE_GT _MMIO(VLV_GUNIT_BASE + 0x2168) #define CHV_FGT_DISABLE_SS0 (1 << 10) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index d67d44611c28..a2e78cf0b5f5 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2945,6 +2945,11 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li /* Wa_18028616096 */ wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3); + + /* + * Wa_14019159160: disable the automatic CCS load balancing + */ + wa_masked_en(wal, GEN12_RCU_MODE, XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE); } if (IS_DG2_G11(i915)) { -- 2.43.0