Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7EB6D1E2834; Wed, 25 Feb 2026 01:38:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771983534; cv=none; b=GTJmLbx1WAsMWPmfqNX5XsHpT0dTNOEAVXbEOfaiT3CkEAwpXYB0TKyK8GIB0rsuaPSdPfMdYhzQeYHeb59HVLY2J2A6iGZZGSepfZXCp7Gn85pRWLGQzWri/XmoZ/g5/NwkHNBxFXEv8oLB9uJRUUxqAEpBqiGgB74rk0+6NJg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771983534; c=relaxed/simple; bh=dJjt3JLLnOZMZ4x7FtHNDe3L4GbHYjmbNw0ZS04+fRY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ok3uL7T2jmnzJV2rcFrG7NH0CSrvT8Nu9N7sH0Fr9iSHdPVuh4DnC6v88b6GuCmIxtU17d2YJXxwuK0/oiRzXQLTFPil0r2SBYJES87XOaGaTFwfFODj2oUIHwuAbE5cznlC95ifIhYeSRXuCqkRNfK4k1L/w6TfIM0VqiI4m6c= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=SKVhP+jh; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="SKVhP+jh" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3DE73C116D0; Wed, 25 Feb 2026 01:38:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1771983534; bh=dJjt3JLLnOZMZ4x7FtHNDe3L4GbHYjmbNw0ZS04+fRY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SKVhP+jhw3Hp7QDmvqSJhDcF63DZV/s9ES6WNR84FZs3JHIpgFzyRmvyvTJeQdTMW m3UuTBddbceJuaXYjKcMQ03UecOgecZIL5M/oduI98YnmJW9IZpKdw9gCLrRuMKcST 8tMMaabOjQKJ5JxYctFs1BH4A1F2+JZn4ZNMISug= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Daniel Machon , Simon Horman , Jakub Kicinski , Sasha Levin Subject: [PATCH 6.19 639/781] net: sparx5/lan969x: fix DWRR cost max to match hardware register width Date: Tue, 24 Feb 2026 17:22:28 -0800 Message-ID: <20260225012415.478694523@linuxfoundation.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260225012359.695468795@linuxfoundation.org> References: <20260225012359.695468795@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.19-stable review patch. If anyone has any objections, please let me know. ------------------ From: Daniel Machon [ Upstream commit 6c28aa8dfdf24f554d4c5d4ff7d723a95360d94a ] DWRR (Deficit Weighted Round Robin) scheduling distributes bandwidth across traffic classes based on per-queue cost values, where lower cost means higher bandwidth share. The SPX5_DWRR_COST_MAX constant is 63 (6 bits) but the hardware register field HSCH_DWRR_ENTRY_DWRR_COST is GENMASK(24, 20), only 5 bits wide (max 31). This causes sparx5_weight_to_hw_cost() to compute cost values that silently overflow via FIELD_PREP, resulting in incorrect scheduling weights. Set SPX5_DWRR_COST_MAX to 31 to match the hardware register width. Fixes: 211225428d65 ("net: microchip: sparx5: add support for offloading ets qdisc") Signed-off-by: Daniel Machon Reviewed-by: Simon Horman Link: https://patch.msgid.link/20260210-sparx5-fix-dwrr-cost-max-v1-1-58fbdbc25652@microchip.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/net/ethernet/microchip/sparx5/sparx5_qos.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_qos.h b/drivers/net/ethernet/microchip/sparx5/sparx5_qos.h index 1231a80335d7b..04f76f1e23f60 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_qos.h +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_qos.h @@ -35,7 +35,7 @@ #define SPX5_SE_BURST_UNIT 4096 /* Dwrr */ -#define SPX5_DWRR_COST_MAX 63 +#define SPX5_DWRR_COST_MAX 31 struct sparx5_shaper { u32 mode; -- 2.51.0