Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D03E23BF9B; Mon, 23 Mar 2026 14:47:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774277257; cv=none; b=tbXV2ZTz7STBoTjz/LBzJXHajaWVt+/531ol4NHpUt1gYwuQj6DCBIuTbd50dQao3OtQSbwkNrOINfXVvyCQuo09nFZTZDMgPp6nfviFD0lTzTZLcJ1ziV/Gy1iMijzYiVfrcYviEr62W4LxQQ7GJwSh1cSW9gGdq1Lt1tAiASM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774277257; c=relaxed/simple; bh=USyR0+2oCRzZaxykn2NX2pSOI6pPtuVeo4e0P3qlcA4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cl0F6/M+r7glWBeBZQIX6c0sCaKRXSXyCpXhzHF7JhFOQ0v1mUGPuq+edd1OBs5BpqJnA1HkGrFGWqnGKi0potJempaUEL54ePNY9kKWwQVHpeD+eafs6TeKEYNAbX/jt446inNyMnsJ/AuNfHTLCytSv2ESOIDmBfLYenkGHqw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=skNPAKx8; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="skNPAKx8" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 870B3C4CEF7; Mon, 23 Mar 2026 14:47:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1774277256; bh=USyR0+2oCRzZaxykn2NX2pSOI6pPtuVeo4e0P3qlcA4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=skNPAKx8heq6/tcZksxXygP0Ta5Fk//N9CLklVu+dVZdl+c8kvwRUP5SBOonPjmZd nKV8dM9lcl7HZxA0Vy1g2WWOKy59JGXqmrTo5MPl4m7DgUvJZ00ZAlO2ABmvMpWwRN mMPyWZLrCmuuYTG/XAqr8XBc46pr7srNU2cHEQNA= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Luke Wang , Adrian Hunter , Ulf Hansson Subject: [PATCH 6.12 336/460] mmc: sdhci: fix timing selection for 1-bit bus width Date: Mon, 23 Mar 2026 14:45:32 +0100 Message-ID: <20260323134534.785735834@linuxfoundation.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260323134526.647552166@linuxfoundation.org> References: <20260323134526.647552166@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.12-stable review patch. If anyone has any objections, please let me know. ------------------ From: Luke Wang commit 5e3486e64094c28a526543f1e8aa0d5964b7f02d upstream. When 1-bit bus width is used with HS200/HS400 capabilities set, mmc_select_hs200() returns 0 without actually switching. This causes mmc_select_timing() to skip mmc_select_hs(), leaving eMMC in legacy mode (26MHz) instead of High Speed SDR (52MHz). Per JEDEC eMMC spec section 5.3.2, 1-bit mode supports High Speed SDR. Drop incompatible HS200/HS400/UHS/DDR caps early so timing selection falls through to mmc_select_hs() correctly. Fixes: f2119df6b764 ("mmc: sd: add support for signal voltage switch procedure") Signed-off-by: Luke Wang Acked-by: Adrian Hunter Cc: stable@vger.kernel.org Signed-off-by: Ulf Hansson Signed-off-by: Greg Kroah-Hartman --- drivers/mmc/host/sdhci.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -4479,8 +4479,15 @@ int sdhci_setup_host(struct sdhci_host * * their platform code before calling sdhci_add_host(), and we * won't assume 8-bit width for hosts without that CAP. */ - if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) + if (host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA) { + host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50); + if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400) + host->caps1 &= ~SDHCI_SUPPORT_HS400; + mmc->caps2 &= ~(MMC_CAP2_HS200 | MMC_CAP2_HS400 | MMC_CAP2_HS400_ES); + mmc->caps &= ~(MMC_CAP_DDR | MMC_CAP_UHS); + } else { mmc->caps |= MMC_CAP_4_BIT_DATA; + } if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23) mmc->caps &= ~MMC_CAP_CMD23;