Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A646A37B00E; Sat, 12 Sep 2026 13:14:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789218879; cv=none; b=qKvbDnQCpXmQZcwin6ikbBlGfyb3I6CTFwWnzUjBUucThvrDYoM0NEB/HVejg6h5TD1gy3tboYye4Vcx1SdDYt7gr/NFTQXBOxvxydh4prEuqOB29keWBobzQcbohKoKs7De7MHqNI+mKUUCKogH1xItH0Ih4xXZk2ltzj6fA5g= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789218879; c=relaxed/simple; bh=5pNOn2z2qiGznVGSTpAuHT41lNZB914+/Am8FcdvG3k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BhelGeSJ+VC+AeyO4d+UBblmWPzLlBJDacO5Wel94Dpu/w4b/FncBu2vb1Tk1mbF3m2HF6UyE/amiO36dVpRmXXR8KF5LKw8NkjNTr7IvkON6jJUq9ftZzCGrr+2zKZJxO7vbTW6I+hhnoNWJVTepTOTx1sRAeTYnVgiGz4woXw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=BnbXfVtm; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="BnbXfVtm" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6BC331F000FF; Sat, 12 Sep 2026 13:14:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1789218878; bh=G/VbgqhjVaTiJPqVqM40ZQ2IvuBF1TGeC/BlysafE0E=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=BnbXfVtm3HBz49GtBn0O3pbFDlg7sryZWKhrkOi2d8nhgR05QFSbYpqa5RZlBstuc 188IBdJxq6+6liYxzG0KLNjGnIPCgW3P1VI3KZq2hrHTkF9Xjy749whSdYIt1ztOh4 tID0NmJoE4MQRVkqV5FaKHLuX5OtxBtyMuFf3IRE= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Biju Das , Thomas Gleixner , Sasha Levin Subject: [PATCH 6.12 1235/1376] irqchip/renesas-rzg2l: Fix loss of interrupt Date: Sat, 12 Sep 2026 09:01:01 +0200 Message-ID: <20260912065635.071257817@linuxfoundation.org> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260912065607.535295758@linuxfoundation.org> References: <20260912065607.535295758@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.12-stable review patch. If anyone has any objections, please let me know. ------------------ From: Biju Das [ Upstream commit 50b10bd0c2d721ad38abd1abe3acdefb6caa0944 ] rzg2l_clear_irq_int() and rzg2l_clear_tint_int() perform a read-modify-write on the ISCR/TSCR status registers to clear the bit for the interrupt just handled. Since these registers are write-0-to-clear per bit, this is racy: If another interrupt's status bit gets set between the read and the write, that bit is written back as 0 by the software-constructed value, clearing an interrupt that hasn't been serviced yet and losing it. This can be reproduced by triggering multiple interrupts at once, e.g.: gpioset -c gpiochip0 355=0 353=0 328=0 352=0 Fix this by writing back only the bit being cleared, with all other bits set to 1, instead of read-modify-writing the whole register. Since 1-bits are left unchanged by hardware, concurrently-set status bits for other interrupts are preserved. Fixes: 3fed09559cd8 ("irqchip: Add RZ/G2L IA55 Interrupt Controller driver") Signed-off-by: Biju Das Signed-off-by: Thomas Gleixner Link: https://patch.msgid.link/20260818110937.5816-1-biju.das.jz@bp.renesas.com Signed-off-by: Sasha Levin --- drivers/irqchip/irq-renesas-rzg2l.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index d83dfc10ff49e..ac88d5aa46c22 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -104,7 +104,7 @@ static void rzg2l_clear_irq_int(struct rzg2l_irqc_priv *priv, unsigned int hwirq * falling/rising-edge. */ if ((iscr & bit) && (iitsr & IITSR_IITSEL_MASK(hw_irq))) { - writel_relaxed(iscr & ~bit, priv->base + ISCR); + writel_relaxed(~bit, priv->base + ISCR); /* * Enforce that the posted write is flushed to prevent that the * just handled interrupt is raised again. @@ -120,7 +120,7 @@ static void rzg2l_clear_tint_int(struct rzg2l_irqc_priv *priv, unsigned int hwir reg = readl_relaxed(priv->base + TSCR); if (reg & bit) { - writel_relaxed(reg & ~bit, priv->base + TSCR); + writel_relaxed(~bit, priv->base + TSCR); /* * Enforce that the posted write is flushed to prevent that the * just handled interrupt is raised again. -- 2.53.0